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features ? 8-bit microcontroller compatible with mcs ? 51 products ? enhanced 8051 architecture ? single-clock cycle per byte fetch ? up to 20 mips throughput at 20 mhz clock frequency ? fully static operation: 0 hz to 20 mhz ? on-chip 2-cycle hardware multiplier ? 16x16 multiply?accumulate unit ? 256x8 internal ram ? 4096x8 internal extra ram ? up to 4kb extended stack in extra ram ? dual data pointers ? 4-level interrupt priority ? nonvolatile program and data memory ? 32k/64k bytes of in-system progra mmable (isp) flash program memory ? 8k bytes of flash data memory ? endurance: minimum 100,000 write/erase cycles ? serial interface for program downloading ? 64-byte fast page programming mode ? 256-byte user signature array ? 2-level program memory lo ck for software security ? in-application programming of program memory ? peripheral features ? three 16-bit enhanced timer/counters ? two 8-bit pwm outputs ? 4-channel 16-bit comp are/capture/pwm array ? enhanced uart with automatic ad dress recognition and framing error detection ? enhanced master/slave spi with double-buffered send/receive ? master/slave two-wire serial interface ? programmable watchdog timer with software reset ? dual analog comparators with selectable interrupts and debouncing ? 8-channel 10-bit adc/dac ? 8 general-purpose interrupt pins ? special microcontroller features ? two-wire on-chip debug interface ? brown-out detection and power-on reset with power-off flag ? active-low external reset pin ? internal rc oscillator ? low power idle and power-down modes ? interrupt recovery from power-down mode ? i/o and packages ? up to 38 programmable i/o lines ? 40-lead pdip or 44-lead tqfp/plcc or 44-pad vqfn/mlf ? configurable i/o modes ? quasi-bidirectional (80c51 style) ? input-only (tristate) ? push-pull cmos output ? open-drain ? operating conditions ? 2.4v to 3.6v v dd voltage range ?-40 c to 85c temperature range ? 0 to 20 mhz @ 2.4?3.6v 8-bit microcontroller with 32k/64k bytes in-system programmable flash at89lp3240 at89lp6440 3706c?micro?2/11
2 3706c?micro?2/11 at89lp3240/6440 1. pin configurations 1.1 40p6: 40-lead pdip 1.2 44a: 44-lead tqfp (top view) 1 2 3 4 5 6 7 8 9 10 11 12 1 3 14 15 16 17 18 19 20 40 3 9 3 8 3 7 3 6 3 5 3 4 33 3 2 3 1 3 0 29 28 27 26 25 24 2 3 22 21 t2/p1.0 t2ex/p1.1 sda/p1.2 scl/p1. 3 ss/p1.4 mosi/p1.5 miso/p1.6 sck/p1.7 rst/p4.2 rxd/p 3 .0 txd/p 3 .1 int0/p 3 .2 int1/p 3 . 3 t0/p 3 .4 t1/p 3 .5 wr/p 3 .6 rd/p 3 .7 xtal2/p4.1 xtal1/p4.0 gnd vdd p0.0/ad0 p0.1/ad1 p0.2/ad2 p0. 3 /ad 3 p0.4/ad4 p0.5/ad5 p0.6/ad6 p0.7/ad7 p4. 3 p4.4/ale p4.5 p2.7/ain 3 /a15 p2.6/ain2/a14 p2.5/ain1/a1 3 p2.4/ain0/a12 p2. 3 /a11/ccd p2.2/a10/ccc p2.1/a9/ccb p2.0/a8/cca 1 2 3 4 5 6 7 8 9 10 11 33 3 2 3 1 3 0 29 28 27 26 25 24 2 3 mosi/p1.5 miso/p1.6 sck/p1.7 rst/p4.2 rxd/p 3 .0 vdd txd/p 3 .1 int0/p 3 .2 int1/p 3 . 3 t0/p 3 .4 t1/p 3 .5 p0.4/ad4 p0.5/ad5 p0.6/ad6 p0.7/ad7 p4. 3 gnd p4.4/ale p4.5 p2.7/ain 3 /a15 p2.6/ain2/a14 p2.5/ain1/a1 3 44 4 3 42 41 40 3 9 3 8 3 7 3 6 3 5 3 4 12 1 3 14 15 16 17 18 19 20 21 22 wr/p 3 .6 rd/p 3 .7 xtal2/p4.1 xtal1/p4.0 gnd gnd cca/a8/p2.0 ccb/a9/p2.1 ccc/a10/p2.2 ccd/a11/p2. 3 a12/ain0/p2.4 p1.4/ss p1. 3 /scl p1.2/sda p1.1/t2ex p1.0/t2 vdd vdd p0.0/ad0 p0.1/ad1 p0.2/ad2 p0. 3 /ad 3
3 3706c?micro?2/11 at89lp3240/6440 1.3 44j: 44-lead plcc 1.4 44m1: 44-pad vqfn/mlf 7 8 9 10 11 12 1 3 14 15 16 17 3 9 3 8 3 7 3 6 3 5 3 4 33 3 2 3 1 3 0 29 mosi/p1.5 miso/p1.6 sck/p1.7 rst/p4.2 rxd/p 3 .0 vdd txd/p 3 .1 int0/p 3 .2 int1/p 3 . 3 t0/p 3 .4 t1/p 3 .5 p0.4/ad4 p0.5/ad5 p0.6/ad6 p0.7/ad7 p4. 3 gnd p4.4/ale p4.5 p2.7/ain 3 /a15 p2.6/ain2/a14 p2.5/ain1/a1 3 6 5 4 3 2 1 44 4 3 42 41 40 18 19 20 21 22 2 3 24 25 26 27 28 wr/p 3 .6 rd/p 3 .7 xtal2/p4.1 xtal1/p4.0 gnd gnd cca/a8/ain0/p2.0 ccb/a9/p2.1 ccc/a10/p2.2 ccd/a11/p2. 3 a12/ain0/p2.4 p1.4/ss p1. 3 /scl p1.2/sda p1.1/t2ex p1.0/t2 vdd vdd p0.0/ad0 p0.1/ad1 p0.2/ad2 p0. 3 /ad 3 1 2 3 4 5 6 7 8 9 10 11 33 3 2 3 1 3 0 29 28 27 26 25 24 2 3 44 4 3 42 41 40 3 9 3 8 3 7 3 6 3 5 3 4 12 1 3 14 15 16 17 18 19 20 21 22 bottom pad should be soldered to ground note: mosi/p1.5 miso/p1.6 sck/p1.7 rst/p4.2 rxd/p 3 .0 vdd txd/p 3 .1 int0/p 3 .2 int1/p 3 . 3 t0/p 3 .4 t1/p 3 .5 p0.4/ad4 p0.5/ad5 p0.6/ad6 p0.7/ad7 p4. 3 gnd p4.4/ale p4.5 p2.7/ain 3 /a15 p2.6/ain2/a14 p2.5/ain1/a1 3 wr/p 3 .6 rd/p 3 .7 xtal2/p4.1 xtal1/p4.0 gnd gnd cca/a8/p2.0 ccb/a9/p2.1 ccc/a10/p2.2 ccd/a11/p2. 3 a12/ain0/p2.4 p1.4/ss p1. 3 /scl p1.2/sda p1.1/t2ex p1.0/t2 vdd vdd p0.0/ad0 p0.1/ad1 p0.2/ad2 p0. 3 /ad 3
4 3706c?micro?2/11 at89lp3240/6440 1.5 pin description table 1-1. at 8 9lp3240/6440 pin de s cription pin number symbol type description tqfp plcc pdip vqfn 1761p1.5 i/o i/o i p1.5 : u s er-config u r ab le i/o port 1 b it 5. mosi : s pi m as ter-o u t/ s l a ve-in. when config u red as m as ter, thi s pin i s a n o u tp u t. when config u red as s l a ve, thi s pin i s a n inp u t. gpi5 : gener a l-p u rpo s e interr u pt inp u t 5. 2 8 72p1.6 i/o i/o i p1.6 : u s er-config u r ab le i/o port 1 b it 6. miso : s pi m as ter-in/ s l a ve-o u t. when config u red as m as ter, thi s pin i s a n inp u t. when config u red as s l a ve, thi s pin i s a n o u tp u t. gpi6 : gener a l-p u rpo s e interr u pt inp u t 6. 39 8 3p1.7 i/o i/o i p1.7 : u s er-config u r ab le i/o port 1 b it 7. sck : s pi clock. when config u red as m as ter, thi s pin i s a n o u tp u t. when config u red as s l a ve, thi s pin i s a n inp u t. gpi7 : gener a l-p u rpo s e interr u pt inp u t 7. 4109 4p4.2 i/o i i p4.2 : u s er-config u r ab le i/o port 4 b it 2 (if re s et f us e i s di sab led). rst : extern a l active-low re s et inp u t (if re s et f us e i s en ab led. s ee ?extern a l re s et? on p a ge 35. ). dcl : s eri a l clock inp u t for on-chip de bu g interf a ce when ocd i s en ab led. 511105p3.0 i/o i p3.0 : u s er-config u r ab le i/o port 3 b it 0. rxd : s eri a l port receiver inp u t. 612 6vdd i su pply volt a ge 713117p3.1 i/o o p3.1 : u s er-config u r ab le i/o port 3 b it 1. txd : s eri a l port tr a n s mitter o u tp u t. 8 14 12 8 p3.2 i/o i p3.2 : u s er-config u r ab le i/o port 3 b it 2. int0 : extern a l interr u pt 0 inp u t or timer 0 g a te inp u t. 915139p3.3 i/o i p3.3 : u s er-config u r ab le i/o port 3 b it 3. int1 : extern a l interr u pt 1 inp u t or timer 1 g a te inp u t 10 16 14 10 p3.4 i/o i/o p3.4 : u s er-config u r ab le i/o port 3 b it 4. t1 : timer/co u nter 0 extern a l inp u t or pwm o u tp u t. 11 17 15 11 p3.5 i/o i/o p3.5 : u s er-config u r ab le i/o port 3 b it 5. t1 : timer/co u nter 1 extern a l inp u t or pwm o u tp u t. 12 1 8 16 12 p3.6 i/o o p3.6 : u s er-config u r ab le i/o port 3 b it 6. wr : extern a l memory interf a ce write s tro b e ( a ctive-low). 13 19 17 13 p3.7 i/o o p3.7 : u s er-config u r ab le i/o port 3 b it 7. rd : extern a l memory interf a ce re a d s tro b e ( a ctive-low). 14 20 1 8 14 p4.1 i/o o o i/o p4.1 : u s er-config u r ab le i/o port 4 b it 1. xtal2 : o u tp u t from inverting o s cill a tor a mplifier. it m a y b e us ed as a port pin if the intern a l rc o s cill a tor i s s elected as the clock s o u rce. clkout : when the intern a l rc o s cill a tor i s s elected as the clock s o u rce, m a y b e us ed to o u tp u t the intern a l clock divided b y 2. dda : s eri a l d a t a inp u t/o u tp u t for on-chip de bu g interf a ce when ocd i s en ab led a nd the extern a l clock i s s elected as the clock s o u rce. 15 21 19 15 p4.0 i/o i i/o p4.0 : u s er-config u r ab le i/o port 4 b it 0. xtal1 : inp u t to the inverting o s cill a tor a mplifier a nd intern a l clock gener a tion circ u it s . it m a y b e us ed as a port pin if the intern a l rc o s cill a tor i s s elected as the clock s o u rce. dda : s eri a l d a t a inp u t/o u tp u t for on-chip de bu g interf a ce when ocd i s en ab led a nd the intern a l rc o s cill a tor i s s elected as the clock s o u rce. 16 22 n/a 16 gnd i gro u nd
5 3706c?micro?2/11 at89lp3240/6440 17 23 20 17 gnd i gro u nd 1 8 24 21 1 8 p2.0 i/o i/o o p2.0 : u s er-config u r ab le i/o port 2 b it 0. cca : timer 2 ch a nnel a comp a re o u tp u t or c a pt u re inp u t. a8 : extern a l memory interf a ce addre ss b it 8 . 19 25 22 19 p2.1 i/o i/o o p2.1 : u s er-config u r ab le i/o port 2 b it 1. ccb : timer 2 ch a nnel b comp a re o u tp u t or c a pt u re inp u t. a9 : extern a l memory interf a ce addre ss b it 9. 20 26 23 20 p2.1 i/o i/o o o p2.2 : u s er-config u r ab le i/o port 2 b it 2. ccc : timer 2 ch a nnel c comp a re o u tp u t or c a pt u re inp u t. a10 : extern a l memory interf a ce addre ss b it 10. da- : dac neg a tive differenti a l o u tp u t. 21 27 24 21 p2.3 i/o i/o o o p2.3 : u s er-config u r ab le i/o port 2 b it 3. ccd : timer 2 ch a nnel d comp a re o u tp u t or c a pt u re inp u t. a11 : extern a l memory interf a ce addre ss b it 11. d+- : dac po s itive differenti a l o u tp u t. 22 2 8 25 22 p2.4 i/o i o p2.4 : u s er-config u r ab le i/o port 2 b it 5. ain0 : an a log comp a r a tor inp u t 0. a12 : extern a l memory interf a ce addre ss b it 12. 23 29 26 23 p2.5 i/o i o p2.5 : u s er-config u r ab le i/o port 2 b it 5. ain1 : an a log comp a r a tor inp u t 1. a13 : extern a l memory interf a ce addre ss b it 13. 24 30 27 24 p2.6 i/o i o p2.6 : u s er-config u r ab le i/o port 2 b it 6. ain2 : an a log comp a r a tor inp u t 2. a14 : extern a l memory interf a ce addre ss b it 14. 25 31 2 8 25 p2.7 i/o i o p2.7 : u s er-config u r ab le i/o port 2 b it 7. ain3 : an a log comp a r a tor inp u t 3. a15 : extern a l memory interf a ce addre ss b it 15. 26 32 29 26 p4.5 i/o p4.5 : u s er-config u r ab le i/o port 4 b it 5. 27 33 30 27 p4.4 i/o o p4.4 : u s er-config u r ab le i/o port 4 b it 4. ale : extern a l memory interf a ce addre ss l a tch en ab le. 2 8 34 2 8 gnd i gro u nd 29 35 31 29 p4.3 i/o i/o p4.3 : u s er-config u r ab le i/o port 4 b it 3. dda : s eri a l d a t a inp u t/o u tp u t for on-chip de bu g interf a ce when ocd i s en ab led a nd the cry s t a l o s cill a tor i s s elected as the clock s o u rce. 30 36 32 30 p0.7 i/o o i p0.7 : u s er-config u r ab le i/o port 0 b it 7. ad7 : extern a l memory interf a ce addre ss /d a t a b it 7. adc7 : adc a n a log inp u t 7. 31 37 33 31 p0.6 i/o o i p0.6 : u s er-config u r ab le i/o port 0 b it 6. ad6 : extern a l memory interf a ce addre ss /d a t a b it 6. adc6 : adc a n a log inp u t 6. 32 3 8 34 32 p0.5 i/o o i p0.5 : u s er-config u r ab le i/o port 0 b it 5. ad5 : extern a l memory interf a ce addre ss /d a t a b it 5. adc5 : adc a n a log inp u t 5. 33 39 35 33 p0.4 i/o o i p0.4 : u s er-config u r ab le i/o port 0 b it 4. ad4 : extern a l memory interf a ce addre ss /d a t a b it 4. adc4 : adc a n a log inp u t 4. 34 40 36 34 p0.3 i/o o i p0.3 : u s er-config u r ab le i/o port 0 b it 3. ad3 : extern a l memory interf a ce addre ss /d a t a b it 3. adc3 : adc a n a log inp u t 3. table 1-1. at 8 9lp3240/6440 pin de s cription pin number symbol type description tqfp plcc pdip vqfn
6 3706c?micro?2/11 at89lp3240/6440 2. overview the at 8 9lp3240/6440 i s a low-power, high-perform a nce cmo s 8 - b it microcontroller with 32k/64k b yte s of in- s y s tem progr a mm ab le fl as h progr a m memory a nd 8 k b yte s of fl as h d a t a memory. the device i s m a n u f a ct u red us ing atmel ? ' s high-den s ity nonvol a tile memory technol- ogy a nd i s comp a ti b le with the ind us try- s t a nd a rd 8 051 in s tr u ction s et. the at 8 9lp3240/6440 i s bu ilt a ro u nd a n enh a nced cpu core th a t c a n fetch a s ingle b yte from memory every clock cycle. in the cl ass ic 8 051 a rchitect u re, e a ch fetch req u ire s 6 clock cycle s , forcing in s tr u ction s to exe- c u te in 12, 24 or 4 8 clock cycle s . in the at 8 9lp3240/6440 cpu, s t a nd a rd in s tr u ction s need only 1 to 4 clock cycle s providing 6 to 12 time s more thro u ghp u t th a n the s t a nd a rd 8 051. s eventy percent of in s tr u ction s need only as m a ny clock cycle s as they h a ve b yte s to exec u te, a nd mo s t of the rem a ining in s tr u ction s req u ire only one a ddition a l clock. the enh a nced cpu core i s c a p a - b le of 20 mip s thro u ghp u t where as the cl ass ic 8 051 cpu c a n deliver only 4 mip s a t the sa me c u rrent con su mption. conver s ely, a t the sa me thro u ghp u t as the cl ass ic 8 051, the new cpu core r u n s a t a m u ch lower s peed a nd there b y gre a tly red u cing power con su mption a nd emi. the at 8 9lp3240/6440 provide s the following s t a nd a rd fe a t u re s : 32k/64k b yte s of in- s y s tem progr a mm ab le fl as h progr a m memory, 8 k b yte s of fl as h d a t a memory, 4352 b yte s of ram, u p to 3 8 i/o line s , three 16- b it timer/co u nter s , u p to s ix pwm o u tp u t s , a progr a mm ab le w a tchdog timer, two a n a log comp a r a tor s , a 10- b it adc/dac with 8 inp u t ch a nnel s , a f u ll-d u plex s eri a l port, a s eri a l peripher a l interf a ce, a two-wire s eri a l interf a ce, a n intern a l rc o s cill a tor, on-chip cry s t a l o s cill a tor, a nd a fo u r-level, twelve-vector interr u pt s y s tem. a b lock di a gr a m i s s hown in fig u re 2- 1 . 35 41 37 35 p0.2 i/o o i p0.2 : u s er-config u r ab le i/o port 0 b it 2. ad2 : extern a l memory interf a ce addre ss /d a t a b it 2. adc2 : adc a n a log inp u t 2. 36 42 3 8 36 p0.1 i/o o i p0.1 : u s er-config u r ab le i/o port 0 b it 1. ad1 : extern a l memory interf a ce addre ss /d a t a b it 1. adc1 : adc a n a log inp u t 1. 37 43 39 37 p0.0 i/o o i p0.0 : u s er-config u r ab le i/o port 0 b it 0. ad0 : extern a l memory interf a ce addre ss /d a t a b it 0. adc0 : adc a n a log inp u t 0. 3 8 44 40 3 8 vdd i su pply volt a ge 39 1 39 vdd i su pply volt a ge 40 2 1 40 p1.0 i/o i/o i p1.0 : u s er-config u r ab le i/o port 1 b it 0. t2 : timer 2 extern a l inp u t or clock o u tp u t. gpi0 : gener a l-p u rpo s e interr u pt inp u t 0. 41 3 2 41 p1.1 i/o i i p1.1 : u s er-config u r ab le i/o port 1 b it 1. t2ex : timer 2 extern a l c a pt u re/relo a d inp u t. gpi1 : gener a l-p u rpo s e interr u pt inp u t 1 42 4 3 42 p1.2 i/o i p1.2 : u s er-config u r ab le i/o port 1 b it 2. gpi2 : gener a l-p u rpo s e interr u pt inp u t 2. 43 5 4 43 p1.3 i/o i p1.3 : u s er-config u r ab le i/o port 1 b it 3. gpi3 : gener a l-p u rpo s e interr u pt inp u t 3. 44 6 5 44 p1.4 i/o i i p1.4 : u s er-config u r ab le i/o port 1 b it 4. ss : s pi s l a ve- s elect. gpi6 : gener a l-p u rpo s e interr u pt inp u t 4. table 1-1. at 8 9lp3240/6440 pin de s cription pin number symbol type description tqfp plcc pdip vqfn
7 3706c?micro?2/11 at89lp3240/6440 timer 0 a nd timer 1 in the at 8 9lp3240/6440 a re enh a nced with two new mode s . mode 0 c a n b e config u red as a v a ri ab le 9- to 16- b it timer/co u nter a nd mode 1 c a n b e config u red as a 16- b it au to-relo a d timer/co u nter. in a ddition, the timer/co u nter s m a y e a ch independently drive a n 8 - b it preci s ion p u l s e width mod u l a tion o u tp u t. timer 2 on the at 8 9lp3240/6440 s erve s as a 16- b it time bas e for a 4-ch a nnel comp a re/c a p- t u re arr a y with u p to fo u r m u lti-ph as ic, v a ri ab le preci s ion ( u p to 16- b it) pwm o u tp u t s . the enh a nced uart of the at 8 9lp3240/6440 incl u de s fr a ming error detection a nd a u tom a tic addre ss recognition. in a ddition, enh a ncement s to mode 0 a llow h a rdw a re a cceler a ted em u l a - tion of h a lf-d u plex s pi or two wire interf a ce s . the i/o port s of the at 8 9lp3240/6440 c a n b e independently config u red in one of fo u r oper a ting mode s . in q uas i- b idirection a l mode, the port s oper a te as in the cl ass ic 8 051. in inp u t-only mode, the port s a re tri s t a ted. p us h-p u ll o u tp u t mode provide s f u ll cmo s driver s a nd open-dr a in mode provide s j us t a p u ll-down. in a ddition, a ll 8 pin s of port 1 c a n b e config u red to gener a te a n inter- r u pt us ing the gener a l-p u rpo s e interr u pt interf a ce. 2.1 block diagram figure 2-1. at 8 9lp3240/6440 block di a gr a m 3 2k/64k bytes flash code p o r t 2 configu r a b le i/ o p o r t 1 configu r a b le i/ o u a r t spi timer 0 timer 1 dual analog comparators w atchdo g timer internal rc oscillator gene r al-pu r pos e inter r up t configu r a b l e oscillator c r ystal o r resonator 8k bytes flash data p o r t 4 configu r a b le i/ o p o r t 3 configu r a b le i/ o timer 2 compare/ capture array p o r t 0 configu r a b le i/ o twi 8-channel 10-bit adc/dac 8 256 bytes ram 4k bytes eram xram interface 8051 single cycle cpu por bod dual data pointers multiply accumulate (16 x 16) on-chip debug
8 3706c?micro?2/11 at89lp3240/6440 2.2 system configuration the at 8 9lp3240/6440 su pport s s ever a l s y s tem config u r a tion option s . nonvol a tile option s a re s et thro u gh us er f us e s th a t m us t b e progr a mmed thro u gh the fl as h progr a mming interf a ce. vol a - tile option s a re controlled b y s oftw a re thro u gh individ ua l b it s of s peci a l f u nction regi s ter s ( s fr s ). the at 8 9lp3240/6440 m us t b e properly config u red b efore correct oper a tion c a n occ u r. 2.2.1 fuse options t ab le 2-1 li s t s the f usab le option s for the at 8 9lp3240/6440. the s e option s m a int a in their s t a te even when the device i s powered off, bu t c a n only b e ch a nged with a n extern a l device progr a m- mer. for more inform a tion, s ee s ection 25.7 ?u s er config u r a tion f us e s ? on p a ge 164 . 2.2.2 software options t ab le 2-2 li s t s s ome import a nt s oftw a re config u r a tion b it s th a t a ffect oper a tion a t the s y s tem level. the s e c a n b e ch a nged b y the a pplic a tion s oftw a re bu t a re s et to their def au lt v a l u e s u pon a ny re s et. mo s t peripher a l s a l s o h a ve m u ltipe config u r a tion b it s th a t a re not li s ted here. table 2-1. u s er config u r a tion f us e s fuse name description clock s o u rce s elect s b etween the high s peed cry s t a l o s cill a tor, low s peed cry s t a l o s cill a tor, extern a l clock or intern a l rc o s cill a tor for the s o u rce of the s y s tem clock. s t a rt- u p time s elect s time-o u t del a y for the por/bod/pwd w a ke- u p period. re s et pin en ab le config u re s the r s t pin as a re s et inp u t or gener a l p u rpo s e i/o brown-o u t detector en ab le en ab le s or di sab le s the brown-o u t detector on-chip de bu g en ab le en ab le s or di sab le s on-chip de bu g. ocd m us t b e en ab led prior to us ing a n in-circ u it de bu gger with the device. in- s y s tem progr a mming en ab le en ab le s or di sab le s in- s y s tem progr a mming. u s er s ign a t u re progr a mming en ab le en ab le s or di sab le s progr a mming of u s er s ign a t u re a rr a y. def au lt port s t a te config u re s the def au lt port s t a te as inp u t-only mode (tri s t a ted) or q uas i- b idirection a l mode (we a kly p u lled high). in-applic a tion progr a mming en ab le en ab le s or di sab led in-applic a tion ( s elf) progr a mming table 2-2. import a nt s oftw a re config u r a tion bit s bit(s) sfr location description pxm0.y pxm1.y p0m0, p0m1, p1m0, p1m1, p2m0, p2m1, p3m0, p3m1, p4m0, p4m1 config u re s the i/o mode of port x pin y to b e one of inp u t-only, q uas i- b idirection a l, p us h-p u ll o u tp u t or open-dr a in. the def au lt s t a te i s controlled b y the def au lt port s t a te f us e ab ove cdv 2-0 clkreg.3-1 s elect s the divi s ion r a tio b etween the o s cill a tor a nd the s y s tem clock tp s 3-0 clkreg.7-4 s elect s the divi s ion r a tio b etween the s y s tem clock a nd the timer s ale s auxr.0 en ab le s /di sab le s toggling of ale exram auxr.1 en ab le s /di sab le s a cce ss to on-chip memorie s th a t a re m a pped to the extern a l d a t a memory a ddre ss s p a ce w s 1-0 auxr.3-2 s elect s the n u m b er of w a it s t a te s when a cce ss ing extern a l d a t a memory x s tk auxr.4 congif u re s the h a rdw a re s t a ck to b e in ram or extr a ram dmen memcon.3 en ab le s /di sab le s a cce ss to the on-chip fl as h d a t a memory iap memcon.7 en b le s /di sab le s the s elf progr a mming fe a t u re when the f us e a llow s
9 3706c?micro?2/11 at89lp3240/6440 2.3 comparison to standard 8051 the at 8 9lp3240/6440 i s p a rt of a f a mily of device s with enh a nced fe a t u re s th a t a re f u lly b in a ry comp a ti b le with the 8 051 in s tr u ction s et. in a ddition, mo s t s fr a ddre ss e s , b it ass ignment s , a nd pin a ltern a te f u nction s a re identic a l to atmel' s exi s ting s t a nd a rd 8 051 prod u ct s . however, d u e to the high perform a nce n a t u re of the device, s ome s y s tem b eh a vior s a re different from tho s e of atmel' s s t a nd a rd 8 051 prod u ct s su ch as at 8 9 s 52 or at 8 9c2051. the m a jor difference s from the s t a nd a rd 8 051 a re o u tlined in the following p a r a gr a ph s a nd m a y b e us ef u l to us er s migr a ting to the at 8 9lp3240/6440 from older device s . 2.3.1 system clock the m a xim u m cpu clock freq u ency eq ua l s the extern a lly su pplied xtal1 freq u ency. the o s cil- l a tor i s not divided b y 2 to provide the intern a l clock a nd x2 mode i s not su pported. the s y s tem clock divider c a n s c a le the cpu clock ver sus the o s cill a tor s o u rce ( s ee s ection 6.5 on p a ge 32 ). 2.3.2 reset the r s t pin of the at 8 9lp3240/6440 i s active-low as comp a red with the a ctive-high re s et in the s t a nd a rd 8 051. in a ddition, the r s t pin i s sa mpled every clock cycle a nd m us t b e held low for a minim u m of two clock cycle s , in s te a d of 24 clock cycle s , to b e recognized as a v a lid re s et. 2.3.3 instruction execution with single-cycle fetch the cpu fetche s one code b yte from memory every clock cycle in s te a d of every s ix clock cycle s . thi s gre a tly incre as e s the thro u ghp u t of the cpu. a s a con s eq u ence, the cpu no longer exec u te s in s tr u ction s in 12, 24 or 4 8 clock cycle s . e a ch s t a nd a rd in s tr u ction exec u te s in only 1 to 4 clock cycle s . s ee ?in s tr u ction s et su mm a ry? on p a ge 143 for more det a il s . any s oftw a re del a y loop s or in s tr u ction- bas ed timing oper a tion s m a y need to b e ret u ned to a chieve the de s ired re su lt s . 2.3.4 interrupt handling the interr u pt controller poll s the interr u pt fl a g s d u ring the l as t clock cycle of a ny in s tr u ction. in order for a n interr u pt to b e s erviced a t the end of a n in s tr u ction, it s fl a g need s to h a ve b een l a tched as a ctive d u ring the next to l as t clock cycle of the in s tr u ction, or in the l as t clock cycle of the previo us in s tr u ction if the c u rrent in s tr u ction exec u te s in only a s ingle clock cycle. the extern a l interr u pt pin s , int0 a nd int1 , a re sa mpled a t every clock cycle in s te a d of once every 12 clock cycle s . co u pled with the s horter in s tr u ction timing a nd f as ter interr u pt re s pon s e, thi s le a d s to a higher m a xim u m r a te of incidence for the extern a l interr u pt s . the s eri a l peripher a l interf a ce ( s pi) h as a dedic a ted interr u pt vector. the s pi no longer s h a re s it s interr u pt with the s eri a l port a nd the e s pi (ie2.2) b it repl a ce s s pie ( s pcr.7). 2.3.5 timer/counters by def au lt timer0, timer 1 a nd timer 2 a re incremented a t a r a te of once per clock cycle. thi s comp a re s to once every 12 clock s in the s t a nd a rd 8 051. a common pre s c a ler i s a v a il ab le to divide the time bas e for a ll timer s a nd red u ce the increment r a te. the tp s 3-0 b it s in the clkreg s fr control the pre s c a ler ( t ab le 6-2 on p a ge 33 ). s etting tp s 3-0 = 1011b will c aus e the timer s to co u nt once every 12 clock s . the extern a l timer/co u nter pin s , t0, t1, t2 a nd t2ex, a re sa mpled a t every clock cycle in s te a d of once every 12 clock cycle s . thi s incre as e s the m a xim u m r a te a t which the co u nter mod u le s m a y f u nction.
10 3706c?micro?2/11 at89lp3240/6440 there i s no difference in co u nting r a te b etween timer 2? s a u to-relo a d/c a pt u re a nd b au d r a te/clock o u t mode s . all mode s increment the timer once per clock cycle. timer 2 in a u to- relo a d/c a pt u re mode increment s a t 12 time s the r a te of s t a nd a rd 8 051 s . s etting tp s 3-0 = 1101b will force timer 2 to co u nt every twelve clock s . timer 2 in b au d r a te or clock o u t mode increment s a t twice the r a te of s t a nd a rd 8 051 s . s etting tp s 3-0 = 0001b will force timer 2 to co u nt every two clock s . 2.3.6 serial port the bau d r a te of the uart in mode 0 def au lt s to 1/4 the clock freq u ency, comp a red to 1/12 the clock freq u ency in the s t a nd a rd 8 051. in s ho u ld a l s o b e noted th a t when us ing timer 1 to gener- a te the bau d r a te in uart mode s 1 or 3, the timer co u nt s a t the clock freq u ency a nd not a t 1/12 the clock freq u ency. to m a int a in the sa me bau d r a te in the at 8 9lp3240/6440 while r u nning a t the sa me freq u ency as a s t a nd a rd 8 051, the time-o u t period m us t b e 12 time s longer. mode 1 of timer 1 su pport s 16- b it au to-relo a d to f a cilit a te longer time-o u t period s for gener a ting low bau d r a te s . timer 2 gener a ted bau d r a te s a re twice as f as t in the at 8 9lp3240/6440 th a n on s t a nd a rd 8 051 s when oper a ting a t the sa me freq u ency. the timer pre s c a ler c a n a l s o s c a le the bau d r a te to m a tch a n exi s ting a pplic a tion. 2.3.7 spi the s eri a l peripher a l interf a ce ( s pi) h as a dedic a ted interr u pt vector. the e s pi (ie2.2) b it repl a ce s s pie ( s pcr.7). s pcr.7 (t s ck) now en ab le s timer-gener a ted bau d r a te. the s pi incl u de s mode f au lt detection. if m u ltiple-m as ter c a p ab ilitie s a re not req u ired, ss ig ( s p s r.2) m us t b e s et to one for m as ter mode to f u nction correctly when ss (p1.4) i s a gener a l p u rpo s e i/o. 2.3.8 watchdog timer the w a tchdog timer in at 8 9lp3240/6440 co u nt s a t a r a te of once per clock cycle. thi s com- p a re s to once every 12 clock s in the s t a nd a rd 8 051. a common pre s c a ler i s a v a il ab le to divide the time bas e for a ll timer s a nd red u ce the co u nting r a te. 2.3.9 i/o ports the i/o port s of the at 8 9lp3240/6440 m a y b e config u red in fo u r different mode s . by def au lt a ll the i/o port s revert to inp u t-only (tri s t a ted) mode a t power- u p or re s et. in the s t a nd a rd 8 051, a ll port s a re we a kly p u lled high d u ring power- u p or re s et. to en ab le 8 051-like port s , the port s m us t b e p u t into q uas i- b idirection a l mode b y cle a ring the p1m0, p2m0, p3m0 a nd p4m0 s fr s . the us er c a n a l s o config u re the port s to s t a rt in q uas i- b idirection a l mode b y di sab ling the tri s t a te- port u s er f us e. when thi s f us e i s di sab led, p1m0, p2m0, p3m0 a nd p4m0 will re s et to 00h in s te a d of ffh a nd the port s will b e we a kly p u lled high. port 0 a nd the u pper ni bb le of port 2 a lw a y s power u p tri s t a ted reg a rdle ss of the f us e s etting d u e to their a n a log f u nction s . 2.3.10 external memory interface the at 8 9lp3240/6440 doe s not su pport extern a l progr a m memory. the p s en a nd ea f u nc- tion s a re not su pported a nd tho s e pin s a re repl a ced with gener a l p u rpo s e i/o. the ale s tro b e doe s not toggle contin u o us ly a nd c a nnot b e us ed as a b o a rd-level clock.
11 3706c?micro?2/11 at89lp3240/6440 3. memory organization the at 8 9lp3240/6440 us e s a h a rv a rd architect u re with s ep a r a te a ddre ss s p a ce s for progr a m a nd d a t a memory. the progr a m memory h as a reg u l a r line a r a ddre ss s p a ce with su pport for 64k b yte s of directly a ddre ssab le a pplic a tion code. the d a t a memory h as 256 b yte s of intern a l ram a nd 12 8 b yte s of s peci a l f u nction regi s ter i/o s p a ce. the at 8 9lp3240/6440 su pport s extern a l d a t a memory with portion s of the extern a l d a t a memory s p a ce implemented on chip as extr a ram a nd nonvol a tile fl as h d a t a memory. extern a l progr a m memory i s not su pported. the mem- ory a ddre ss s p a ce s of the at 8 9lp3240/6440 a re li s ted in t ab le 3-1 . 3.1 program memory the at 8 9lp3240/6440 cont a in s 32k/64k b yte s of on-chip in- s y s tem progr a mm ab le fl as h memory for progr a m s tor a ge. the fl as h memory h as a n end u r a nce of a t le as t 100,000 write/er as e cycle s a nd a minim u m d a t a retention time of 10 ye a r s . the re s et a nd interr u pt vec- tor s a re loc a ted within the fir s t 8 3 b yte s of progr a m memory (refer to t ab le 9-1 on p a ge 41 ). con s t a nt t ab le s c a n b e a lloc a ted within the entire 32k/64k progr a m memory a ddre ss s p a ce for a cce ss b y the movc in s tr u ction. the at 8 9lp3240/6440 doe s not su pport extern a l progr a m memory. a m a p of the at 8 9lp3240/6440 progr a m memory i s s hown in fig u re 3-1 . 3.1.1 sig in a ddition to the 64k code s p a ce, the at 8 9lp3240/6440 a l s o su pport s a 256- b yte u s er s ign a - t u re arr a y a nd a 12 8 - b yte atmel s ign a t u re arr a y th a t a re a cce ss i b le b y the cpu. the atmel s ign a t u re arr a y i s initi a lized with the device id in the f a ctory. the s econd p a ge of the u s er s ig- n a t u re arr a y (01 8 0h?01ffh) i s initi a lized with a n a log config u r a tion d a t a incl u ding the intern a l rc o s cill a tor c a li b r a tion b yte. the u s er s ign a t u re arr a y i s a v a il ab le for us er identific a tion code s or con s t a nt p a r a meter d a t a . d a t a s tored in the s ign a t u re a rr a y i s not s ec u re. s ec u rity b it s will di sab le write s to the a rr a y; however, re a d s b y a n extern a l device progr a mmer a re a lw a y s a llowed. in order to re a d from the s ign a t u re a rr a y s , the s igen b it (dpcf.3) m us t b e s et ( s ee t ab le 5-5 on p a ge 2 8 ). while s igen i s one, movc a,@a+dptr will a cce ss the s ign a t u re a rr a y s . the u s er s ign a t u re arr a y i s m a pped from a ddre ss e s 0100h to 01ffh a nd the atmel s ign a t u re arr a y i s m a pped from a ddre ss e s 0000h to 007fh. s igen m us t b e cle a red b efore us ing movc to a cce ss the code memory. the u s er s ign a t u re arr a y m a y a l s o b e modified b y the in-applic a tion progr a mming interf a ce. when iap = 1 a nd s igen = 1, movx @dptr in s tr u ction s will a cce ss the a rr a y ( s ee s ection 3.5 on p a ge 21 ). table 3-1. at 8 9lp3240/6440 memory addre ss s p a ce s name description range data directly a ddre ssab le intern a l ram 00h?7fh idata indirectly a ddre ssab le intern a l ram a nd s t a ck s p a ce 00h?ffh s fr directly a ddre ssab le i/o regi s ter s p a ce 8 0h?ffh edata on-chip extr a ram a nd extended s t a ck s p a ce 0000h?0fffh fdata on-chip nonvol a tile fl as h d a t a memory 1000h?2fffh xdata extern a l d a t a memory 3000h?ffffh code on-chip nonvol a tile fl as h progr a m memory (at 8 9lp3240) 0000h?7fffh on-chip nonvol a tile fl as h progr a m memory (at 8 9lp6440) 0000h?ffffh s ig on-chip nonvol a tile fl as h s ign a t u re a rr a y 0000h?01ffh
12 3706c?micro?2/11 at89lp3240/6440 figure 3-1. progr a m memory m a p 3.2 internal data memory the at 8 9lp3240/6440 cont a in s 256 b yte s of gener a l s ram d a t a memory pl us 12 8 b yte s of i/o memory m a pped into a s ingle 8 - b it a ddre ss s p a ce. acce ss to the intern a l d a t a memory doe s not req u ire a ny config u r a tion. the intern a l d a t a memory h as three a ddre ss s p a ce s : data, idata a nd s fr; as s hown in fig u re 3-2 . s ome portion s of extern a l d a t a memory a re a l s o implemented intern a lly. s ee ?extern a l d a t a memory? b elow for more inform a tion. figure 3-2. intern a l d a t a memory m a p 3.2.1 data the fir s t 12 8 b yte s of ram a re directly a ddre ssab le b y a n 8 - b it a ddre ss (00h?7fh) incl u ded in the in s tr u ction. the lowe s t 32 b yte s of data memory a re gro u ped into 4 ba nk s of 8 regi s ter s e a ch. the r s 0 a nd r s 1 b it s (p s w.3 a nd p s w.4) s elect which regi s ter ba nk i s in us e. in s tr u c- tion s us ing regi s ter a ddre ss ing will only a cce ss the c u rrently s pecified ba nk. the lower 12 8 b it a ddre ss e s a re a l s o m a pped into data a ddre ss e s 20h?2fh. program memory 0000 ffff 0000 007f user signature array 0100 01ff atmel signature array sigen=0 sigen=1 at89lp6440 program memory 0000 7fff 0000 007f user signature array 0100 01ff atmel signature array at89lp3240 ffh upper 128 80h 7fh lower 128 0 accessible by direct addressing ffh 80h accessible by direct and indirect addressing special function registers ports status and control bits registers stack pointer accumulator (etc.) timers accessible by indirect addressing only idata sfr data/idata
13 3706c?micro?2/11 at89lp3240/6440 3.2.2 idata the f u ll 256 b yte intern a l ram c a n b e indirectly a ddre ss ed us ing the 8 - b it pointer s r0 a nd r1. the fir s t 12 8 b yte s of idata incl u de the data s p a ce. the h a rdw a re s t a ck i s a l s o loc a ted in the idata s p a ce when x s tk = 0. 3.2.3 sfr the u pper 12 8 direct a ddre ss e s ( 8 0h?ffh) a cce ss the i/o regi s ter s . i/o regi s ter s on at 8 9lp device s a re referred to as s peci a l f u nction regi s ter s . the s fr s c a n only b e a cce ss ed thro u gh direct a ddre ss ing. all s fr loc a tion s a re not implemented. s ee s ection 4. for a li s ted of a v a il ab le s fr s . 3.3 external data memory at 8 9lp microcontroller s su pport a 16- b it extern a l memory a ddre ss s p a ce for u p to 64k b yte s of extern a l d a t a memory (xdata). the extern a l memory s p a ce i s a cce ss ed with the movx in s tr u ction s . s ome intern a l d a t a memory re s o u rce s a re m a pped into portion s of the extern a l a ddre ss s p a ce as s hown in fig u re 3-3 . the s e memory s p a ce s m a y req u ire config u r a tion b efore the cpu c a n a cce ss them. the at 8 9lp3240/6440 incl u de s 4k b yte s of on-chip extr a ram (edata) a nd 8 k b yte s of nonvol a tile fl as h d a t a memory (fdata). figure 3-3. extern a l d a t a memory m a p 3.3.1 xdata the extern a l d a t a memory s p a ce c a n a ccommod a te u p to 64kb of extern a l memory. the at 8 9lp3240/6440 us e s the s t a nd a rd 8 051 extern a l memory interf a ce with the u pper a ddre ss b yte on port 2, the lower a ddre ss b yte a nd d a t a in/o u t m u ltiplexed on port 0, a nd the ale, rd a nd wr s tro b e s . movx in s tr u ction s t a rgeted to xdata req u ire a minim u m of 4 clock cycle s . xdata c a n b e a cce ss ed with b oth 16- b it (movx @dptr) a nd 8 - b it (movx @ri) a ddre ss e s . s ee s ection 3.3.4 on p a ge 17 for more det a il s of the extern a l memory interf a ce. extra ram (edata: 4kb) 0fff 2fff 3000 flash data (fdata: 8kb) 0000 0fff 1000 ffff external data (xdata: 64kb) external data (xdata: 60kb) extra ram (edata: 4kb) external data (xdata: 52kb) ffff ffff 1000 exram = 1 exram = 0 dmen = 0 exram = 0 dmen = 1
14 3706c?micro?2/11 at89lp3240/6440 s ome intern a l d a t a memory s p a ce s a re m a pped into portion s of the xdata a ddre ss s p a ce. in thi s c as e the lower a ddre ss r a nge s will a cce ss intern a l re s o u rce s in s te a d of extern a l memory. addre ss e s ab ove the r a nge implemented intern a lly will def au lt to xdata. the at 8 9lp3240/6440 su pport s u p to 52k or 60k b yte s of extern a l memory when us ing the inter- n a lly m a pped memorie s . s etting the exram b it (auxr.1) to one will force a ll movx in s tr u ction s to a cce ss the entire 64kb xdata reg a rdle ss of their a ddre ss ( s ee ?auxr ? a u xil- i a ry control regi s ter? on p a ge 1 8 ). 3.3.2 edata the extr a ram i s a portion of the extern a l memory s p a ce implemented as a n intern a l 4k b yte au xili a ry ram. the extr a ram i s m a pped into the edata s p a ce a t the b ottom of the extern a l memory a ddre ss s p a ce, from 0000h to 0fffh. movx in s tr u ction s to thi s a ddre ss r a nge will a cce ss the intern a l extr a ram. edata c a n b e a cce ss ed with b oth 16- b it (movx @dptr) a nd 8 - b it (movx @ri) a ddre ss e s . when 8 - b it a ddre ss e s a re us ed, the page regi s ter (0 8 6h) su p- plie s the u pper a ddre ss b it s . the page regi s ter b re a k s edata into s ixteen 256- b yte p a ge s . a p a ge c a nnot b e s pecified independently for movx @r0 a nd movx @r1. s etting page ab ove 0fh en ab le s xdata a cce ss , bu t doe s not ch a nge the v a l u e of port 2. when 16- b it a ddre ss e s a re us ed (dptr), the iap b it (memcon.7) m us t b e zero to a cce ss edata. movx in s tr u ction s to edata req u ire a minim u m of 2 clock cycle s . 3.3.3 fdata the fl as h d a t a memory i s a portion of the extern a l memory s p a ce implemented as a n intern a l nonvol a tile d a t a memory. fl as h d a t a memory i s en ab led b y s etting the dmen b it (memcon.3) to one. when iap = 0 a nd dmen = 1, the fl as h d a t a memory i s m a pped into the fdata s p a ce, directly ab ove the edata s p a ce ne a r the b ottom of the extern a l memory a ddre ss s p a ce, from 1000h to 2fffh. ( s ee fig u re 3-3 ). movx in s tr u ction s to thi s a ddre ss r a nge will a cce ss the intern a l nonvol a tile memory. fdata i s not a cce ss i b le while dmen = 0. fdata c a n b e a cce ss ed only b y 16- b it (movx @dptr) a ddre ss e s . movx @ri in s tr u ction s to the fdata a ddre ss r a nge will a cce ss extern a l memory. addre ss e s ab ove the fdata r a nge a re m a pped to xdata. movx in s tr u ction s to fdata req u ire a minim u m of 4 clock cycle s . 3.3.3.1 write protocol the fdata a ddre ss s p a ce a cce ss e s a n intern a l nonvol a tile d a t a memory. thi s a ddre ss s p a ce c a n b e re a d j us t like edata b y i ssu ing a movx a,@dptr; however, write s to fdata req u ire a more complex protocol a nd t a ke s ever a l milli s econd s to complete. the at 8 9lp3240/6440 us e s a n idle-while-write a rchitect u re where the cpu i s pl a ced in a n idle s t a te while the write occ u r s . when the write complete s , the cpu will contin u e exec u ting with the in s tr u ction a fter the movx @dptr,a in s tr u ction th a t s t a rted the write. all peripher a l s will contin u e to f u nction d u ring the write cycle; however, interr u pt s will not b e s erviced u ntil the writ e complete s . table 3-2. pag e ? edata p a ge regi s ter pa g e = 8 6h re s et v a l u e = 0000 0000b not bit addre ssab le page.7 page.6 page.5 page.4 page.3 page.2 page.1 page.0 bit76543210 symbol function pag e 7-0 s elect s which 256- b yte p a ge of edata i s c u rrently a cce ss i b le b y movx @ri in s tr u ction s when page < 10h. any page v a l u e b etween 10h a nd ffh will s elected xdata; however, thi s v a l u e will not b e o u tp u t on p2.
15 3706c?micro?2/11 at89lp3240/6440 to en ab le write a cce ss to the nonvol a tile d a t a memory, the mwen b it (memcon.4) m us t b e s et to one. when mwen = 1 a nd dmen = 1, movx @dptr,a m a y b e us ed to write to fdata. fdata us e s fl as h memory with a p a ge- bas ed progr a mming model. fl as h d a t a memory differ s from tr a dition a l eeprom d a t a memory in the method of writing d a t a . eeprom gener a lly c a n u pd a te a s ingle b yte with a ny v a l u e. fl as h memory s plit s progr a mming into write a nd er as e oper a tion s . a fl as h write c a n only progr a m zeroe s , i.e ch a nge one s into zeroe s (). any one s in the write d a t a a re ignored. a fl as h er as e s et s a n entire p a ge of d a t a to one s s o th a t a ll b yte s b ecome ffh. therefore a fter a n er as e, e a ch b yte in the p a ge c a n b e written only once with a ny po ss i b le v a l u e. byte s c a n not b e overwritten once they a re ch a nged from the er as ed s t a te witho u t po ss i b ility of corr u pting the d a t a . therefore, if even a s ingle b yte need s u pd a ting; then the content s of the p a ge m us t fir s t b e sa ved, the entire p a ge m us t b e er as ed a nd the zero b it s in a ll b yte s (old a nd new d a t a com b ined) m us t b e written. avoiding u nnece ssa ry p a ge er as e s gre a tly improve s the end u r a nce of the memory. the at 8 9lp3240/6440 incl u de s 64 d a t a p a ge s of 12 8 b yte s e a ch. one or more b yte s in a p a ge m a y b e written a t one time. the at 8 9lp3240/6440 incl u de s a tempor a ry p a ge bu ffer of 64 b yte s , or h a lf of a p a ge. bec aus e the p a ge bu ffer i s 64 b yte s long, the m a xim u m n u m b er of b yte s written a t one time i s 64. therefore, two write cycle s a re req u ired to fill the entire 12 8 - b yte p a ge, one for the low h a lf p a ge (00h?3fh) a nd one for the high h a lf p a ge (40h?7fh) as s hown in fig u re 3-4 . figure 3-4. p a ge progr a mming s tr u ct u re the ldpg b it (memcon.5) a llow s m u ltiple d a t a b yte s to b e lo a ded to the tempor a ry p a ge bu f- fer. while ldpg = 1, movx @dptr,a in s tr u ction s will lo a d d a t a to the p a ge bu ffer, bu t will not s t a rt a write s eq u ence. note th a t a previo us ly lo a ded b yte m us t not b e relo a ded prior to the write s eq u ence. to write the h a lf p a ge into the memory, ldpg m us t fir s t b e cle a red a nd then a movx @dptr,a with the fin a l d a t a b yte i s i ssu ed. the a ddre ss of the fin a l movx determine s which h a lf p a ge will b e written. if a movx @dptr,a in s tr u ction i s i ssu ed while ldpg = 0 with- o u t lo a ding a ny previo us b yte s , only a s ingle b yte will b e written. the p a ge bu ffer i s re s et a fter e a ch write oper a tion. fig u re s 3-5 a nd fig u re 3-6 on p a ge 16 s how the difference b etween b yte write s a nd p a ge write s . the au to-er as e b it aer s (memcon.6) c a n b e s et to one to perform a p a ge er as e au tom a tic a lly a t the b eginning of a ny write s eq u ence. the p a ge er as e will er as e the entire p a ge, i.e. b oth the low a nd high h a lf p a ge s . however, the write oper a tion p a ired with the au to-er as e c a n only pro- gr a m one of the h a lf p a ge s . a s econd write cycle witho u t au to-er as e i s req u ired to u pd a te the other h a lf p a ge. 10 3 f data memory high half page 40 7f 00 3 f page buffer
16 3706c?micro?2/11 at89lp3240/6440 figure 3-5. fdata byte write figure 3-6. fdata p a ge write freq u ently j us t a few b yte s within a p a ge m us t b e u pd a ted while m a int a ining the s t a te of the other b yte s . there a re two option s for h a ndling thi s s it ua tion th a t a llow the fl as h d a t a memory to em u l a te a tr a dition a l eeprom memory. the s imple s t method i s to copy the entire p a ge into a bu ffer a lloc a ted in ram, modify the de s ired b yte loc a tion s in the ram bu ffer, a nd then lo a d a nd write ba ck fir s t the low h a lf p a ge (with au to-er as e) a nd then the high h a lf p a ge to the fl as h mem- ory. thi s option req u ire s th a t a t le as t one p a ge s ize of ram i s a v a il ab le as a tempor a ry bu ffer. the s econd option i s to s tore only one h a lf p a ge in ram. the u nmodified b yte s of the other p a ge a re lo a ded directly into the fl as h memory? s tempor a ry lo a d bu ffer b efore lo a ding the u pd a ted v a l u e s of the modified b yte s . for ex a mple, if j us t the low h a lf p a ge need s modific a tion, the us er m us t fir s t s tore the high h a lf p a ge to ram, followed b y re a ding a nd lo a ding the u n a ffected b yte s of the low h a lf p a ge into the p a ge bu ffer. then the modified b yte s of the low h a lf p a ge a re s tored to the p a ge bu ffer b efore s t a rting the au to-er as e s eq u ence. the s tored v a l u e of the high h a lf p a ge m us t b e written witho u t au to-er as e a fter the progr a mming of the low h a lf p a ge complete s . thi s method red u ce s the a mo u nt of ram req u ired; however, more s oftw a re overhe a d i s needed b ec aus e the re a d- a nd-lo a d- ba ck ro u tine m us t s kip tho s e b yte s in the p a ge th a t need to b e u pd a ted in order to prevent tho s e loc a tion s in the bu ffer from b eing lo a ded with the previo us d a t a , as thi s will b lock the new d a t a from b eing lo a ded correctly. a write s eq u ence will not occ u r if the brown-o u t detector i s a ctive, even if the bod re s et h as b een di sab led. in c as e s where the bod re s et i s di sab led, the us er s ho u ld check the bod s t a t us b y re a ding the wrtinh b it in memcon. if a write c u rrently in progre ss i s interr u pted b y the bod d u e to a low volt a ge condition, the err fl a g will b e s et. fdata c a n a lw a y s b e re a d reg a rd- le ss of the bod s t a te. for more det a il s on us ing the fl as h d a t a memory, s ee the a pplic a tion note titled ?at 8 9lp fl as h d a t a memory?. fdata m a y a l s o b e progr a mmed b y a n extern a l device progr a mmer ( s ee s ec- tion 25. on p a ge 157 ). mwen dmen t wc ldpg idle movx t wc mwen dmen t wc ldpg idle movx
17 3706c?micro?2/11 at89lp3240/6440 3.3.4 external memory interface the at 8 9lp3240/6440 us e s the s t a nd a rd 8 051 extern a l memory interf a ce with the u pper a ddre ss on port 2, the lower a ddre ss a nd d a t a in/o u t m u ltiplexed on port 0, a nd the ale, rd a nd wr s tro b e s . the interf a ce m a y b e us ed in two different config u r a tion s depending on which type of movx in s tr u ction i s us ed to a cce ss xdata. fig u re 3-7 s how s a h a rdw a re config u r a tion for a cce ss ing u p to 64k b yte s of extern a l ram us ing a 16- b it line a r a ddre ss . port 0 s erve s as a m u ltiplexed a ddre ss /d a t a bus to the ram. the addre ss l a tch en ab le s tro b e (ale) i s us ed to l a tch the lower a ddre ss b yte into a n extern a l reg- i s ter s o th a t port 0 c a n b e freed for d a t a inp u t/o u tp u t. port 2 provide s the u pper a ddre ss b yte thro u gho u t the oper a tion. the movx @dptr in s tr u ction s us e line a r addre ss mode figure 3-7. extern a l memory 16- b it line a r addre ss mode table 3-3. memcon ? memory control regi s ter memcon = 96h re s et v a l u e = 0000 00xxb not bit addre ssab le iap aer s ldpg mwen dmen err ? wrtinh bit76543210 symbol function iap in-applic a tion progr a mming en ab le. when iap = 1 a nd the iap f us e i s en ab led, progr a mming of the code/ s ig s p a ce i s en ab led a nd movx @dptr in s tr u ction s will a cce ss code/ s ig in s te a d of edata or fdata. cle a r iap to di sab le progr a mming of code/ s ig a nd a llow a cce ss to edata a nd fdata. aer s a u to-er as e en ab le. s et to perform a n au to-er as e of a fl as h memory p a ge (code, s ig or fdata) d u ring the next write s eq u ence. cle a r to perform write witho u t er as e. ldpg lo a d p a ge en ab le. s et to thi s b it to lo a d m u ltiple b yte s to the tempor a ry p a ge bu ffer. byte loc a tion s m a y not b e lo a ded more th a n once b efore a write. ldpg m us t b e cle a red b efore writing. mwen memory write en ab le. s et to en ab le progr a mming of a nonvol a tile memory loc a tion (code, s ig or fdata). cle a r to di sab le progr a mming of a ll nonvol a tile memorie s . dmen d a t a memory en ab le. s et to en ab le nonvol a tile d a t a memory a nd m a p it into the fdata s p a ce. cle a r to di sab le nonvol a tile d a t a memory. err error fl a g. s et b y h a rdw a re if a n error occ u rred d u ring the l as t progr a mming s eq u ence d u e to a b rowno u t condition (low volt a ge on vdd). m us t b e cle a red b y s oftw a re. wrtinh write inhi b it fl a g. cle a red b y h a rdw a re when the volt a ge on vdd h as f a llen b elow the minim u m progr a mming volt a ge. s et b y h a rdw a re when the volt a ge on vdd i s ab ove the minim u m progr a mming volt a ge. p1 p0 ale p2 rd p 3 wr at89lp data latch external data memory we addr oe
18 3706c?micro?2/11 at89lp3240/6440 fig u re 3- 8 s how s a h a rdw a re config u r a tion for a cce ss ing 256- b yte b lock s of extern a l ram us ing a n 8 - b it p a ged a ddre ss . port 0 s erve s as a m u ltiplexed a ddre ss /d a t a bus to the ram. the ale s tro b e i s us ed to l a tch the a ddre ss b yte into a n extern a l regi s ter s o th a t port 0 c a n b e freed for d a t a inp u t/o u tp u t. the port 2 i/o line s (or other port s ) c a n provide control line s to p a ge the mem- ory; however, thi s oper a tion i s not h a ndled au tom a tic a lly b y h a rdw a re. the s oftw a re a pplic a tion m us t ch a nge the port 2 regi s ter when a ppropri a te to a cce ss different p a ge s . the movx @ri in s tr u ction s us e p a ged addre ss mode. figure 3-8. extern a l memory 8 - b it p a ged addre ss mode note th a t prior to us ing the extern a l memory interf a ce, port 2, wr (p3.6), rd (p3.7) a nd ale (p4.4) m us t b e config u red as o u tp u t s . s ee s ection 10.1 ?port config u r a tion? on p a ge 45 . port 0 i s config u red au tom a tic a lly to p us h-p u ll o u tp u t mode when o u tp u tting a ddre ss or d a t a a nd i s p1 p0 i/o ale p2 rd p 3 wr at89lp data latch external data memory we addr pag e bits oe table 3-4. auxr ? a u xili a ry control regi s ter auxr = 8 eh re s et v a l u e = xxx0 0000b not bit addre ssab le ???x s tk w s 1w s 0 exram ale s bit76543210 symbol function x s tk extended s t a ck en ab le. when x s tk = 0 the s t a ck re s ide s in idata a nd i s limited to 256 b yte s . s et x s tk = 1 to pl a ce the s t a ck in edata for u p to 4k b yte s of extended s t a ck s p a ce. all pu s h, pop, call a nd ret in s tr u ction s will inc u r a one or two cycle pen a lty when a cce ss ing the extended s t a ck. w s [1-0] w a it s t a te s elect. determine s the n u m b er of w a it s t a te s in s erted into extern a l memory a cce ss e s . w s 1 w s 0 w a it s t a te s rd / wr s tro b e width 000 1 x t cyc 011 2 x t cyc 102 3 x t cyc 113 4 x t cyc exram extern a l ram en ab le. when exram = 0, movx in s tr u ction s c a n a cce ss the intern a lly m a pped portion s of the a ddre ss s p a ce. acce ss e s to a ddre ss e s ab ove intern a lly m a pped memory will a cce ss extern a l memory. s et exram = 1 to b yp ass the intern a l memory a nd m a p the entire a ddre ss s p a ce to extern a l memory. ale s ale idle s t a te. when ale s = 0 the idle pol a rity of ale i s high ( a ctive). when ale s = 1 the idle pol a rity of ale i s low (in a ctive). the ale s tro b e p u l s e i s a lw a y s a ctive high. ale s m us t b e zero in order to us e p4.4 as a gener a l i/o.
19 3706c?micro?2/11 at89lp3240/6440 au tom a tic a lly tri s t a ted when inp u tting d a t a reg a rdle ss of the port 0 config u r a tion. the port 0 config u r a tion will determine the idle s t a te of port 0 when not a cce ss ing the extern a l memory. fig u re 3-9 a nd fig u re 3-10 s how ex a mple s of extern a l d a t a memory write a nd re a d cycle s , re s pectively. the a ddre ss on p0 a nd p2 i s s t ab le a t the f a lling edge of ale. the idle pol a rity of ale i s controlled b y ale s (auxr.0). when ale s = 0 the idle pol a rity of ale i s high ( a ctive). when ale s = 1 the idle pol a rity of ale i s low (in a ctive). the ale s tro b e p u l s e i s a lw a y s a ctive high. unlike s t a nd a rd 8 051 s , ale will not to ggle contin u o us ly when not a cce ss ing extern a l memory. ale s m us t b e zero in order to us e p4.4 as a gener a l-p u rpo s e i/o. the w s b it s in auxr c a n extended the rd a nd wr s tro b e s b y 1, 2 or 3 cycle s as s hown in fig u re s 3-11, 3-12 a nd 3-13. if a longer s tro b e i s req u ired, the a pplic a tion c a n s c a le the s y s tem clock with the clock divider to meet the req u irement s ( s ee s ection 6.5 on p a ge 32 ). figure 3-9. extern a l d a t a memory write cycle (w s =00b) figure 3-10. extern a l d a t a memory re a d cycle (w s = 00b) s1 s2 s 3 s4 clk ale ales = 0 ales = 1 wr dpl or ri out p0 sfr p0 sfr p0 p2 sfr p2 sfr dph or p2 out p2 data out s1 s2 s 3 s4 clk ale ales = 0 ales = 1 rd float data sampled dpl or ri out p0 sfr p0 sfr p0 p2 sfr p2 sfr dph or p2 out p2
20 3706c?micro?2/11 at89lp3240/6440 figure 3-11. movx with one w a it s t a te (w s =01b) figure 3-12. movx with two w a it s t a te s (w s =10b) figure 3-13. movx with three w a it s t a te s (w s =11b) 3.4 extended stack the at 8 9lp3240/6440 provide s a n extended s t a ck s p a ce for a pplic a tion s req u iring a ddition a l s t a ck memory. by def au lt the s t a ck i s loc a ted in the 256- b yte idata s p a ce of intern a l d a t a memory. the idata s t a ck i s referenced s olely b y the 8 - b it s t a ck pointer ( s p: 8 1h). s etting the x s tk b it in auxr en ab le s the extended s t a ck. the extended s t a ck re s ide s in the edata s p a ce for u p to 4kb of s t a ck memory. the extended s t a ck i s referenced b y a 12- b it pointer formed from s p a nd the fo u r l s b s of the extended s t a ck pointer ( s px: 9eh) as s hown in fig u re 3-14 . s p i s s h a red b etween b oth s t a ck s . note th a t the s t a nd a rd idata s t a ck will not overflow to the edata s t a ck or vice ver sa . the s t a ck a nd extended s t a ck a re m u t ua lly excl us ive a nd s px i s ignored when xt s k=0. an a pplic a tion choo s ing to s witch b etween s t a ck s b y toggling x s tk m us t m a in- s1 s2 s 3 w1 clk ale wr dpl out p0 sfr p0 sfr p0 p2 sfr p2 sfr dph or p2 out p2 data out s4 rd dpl out p0 sfr p0 sfr p0 float s1 s2 s 3 w1 clk ale wr dpl out p0 sfr p0 sfr p0 p2 sfr p2 sfr dph or p2 out p2 data out w2 rd dpl out p0 sfr p0 sfr p0 float s4 s1 s2 s 3 w1 clk ale wr dpl out p0 sfr p0 sfr p0 p2 sfr p2 sfr dph or p2 out p2 data out w2 rd dpl out p0 sfr p0 sfr p0 float w 3 s4
21 3706c?micro?2/11 at89lp3240/6440 t a in s ep a r a te copie s of s p for us e with e a ch s t a ck s p a ce. interr u pt s s ho u ld b e di sab led while s w a pping copie s of s p in su ch a n a pplic a tion to prevent illeg a l s t a ck a cce ss e s . all interr u pt c a ll s a nd pu s h, pop, acall, lcall, ret a nd reti in s tr u ction s will inc u r a one or two-cycle pen a lty while the extended s t a ck i s en ab led, depending on the n u m b er of s t a ck a cce ss in e a ch in s tr u ction. the extended s t a ck m a y only exi s t within the intern a l edata s p a ce; it c a nnot b e pl a ced in xdata. the s t a ck will contin u e to us e edata even if edata i s di sab led b y s etting exram = 1. figure 3-14. s t a ck config u r a tion s 3.5 in-application programming (iap) the at 8 9lp3240/6440 su pport s in-applic a tion progr a mming (iap), a llowing the progr a m mem- ory to b e modified d u ring exec u tion. iap c a n b e us ed to modify the us er a pplic a tion on the fly or to us e progr a m memory for nonvol a tile d a t a s tor a ge. the sa me p a ge s tr u ct u re write protocol for fdata a l s o a pplie s to iap ( s ee s ection 3.3.3.1 ?write protocol? on p a ge 14 ). the cpu i s a lw a y s pl a ced in idle while modifying the progr a m memory. when the write complete s , the cpu will contin u e exec u ting with the in s tr u ction a fter the movx @dptr,a in s tr u ction th a t s t a rted the write. to en ab le a cce ss to the progr a m memory, the iap b it (memcon.7) m us t b e s et to one a nd the iap u s er f us e m us t b e en ab led. the iap u s er f us e c a n di sab le a ll iap oper a tion s . when thi s f us e i s di sab led, the iap b it will b e forced to 0. while iap i s en ab led, a ll movx @dptr in s tr u c- tion s will a cce ss the code s p a ce in s te a d of edata/fdata/xdata. iap a l s o a llow s reprogr a mming of the u s er s ign a t u re arr a y when s igen = 1. the iap a cce ss s etting s a re su m- m a rized in t ab le 3-5 . 70 00h ffh i data (256) sp 70 00h fffh e data (4k) sp 30 spx xstk = 0 xstk = 1 table 3-5. iap acce ss s etting s iap sigen dmen movx @dptr movc @dptr 0 0 0 edata (0000?0fffh) code (0000?ffffh) 0 0 1 fdata (1000?2fffh) code (0000?ffffh) 0 1 0 edata (0000?0fffh) s ig (0000?01ffh) 0 1 1 fdata (1000?2fffh) s ig (0000?01ffh) 1 0 x code (0000?ffffh) code (0000?ffffh) 11x s ig (0000?01ffh) s ig (0000?01ffh)
22 3706c?micro?2/11 at89lp3240/6440 4. special function registers a m a p of the on-chip memory a re a c a lled the s peci a l f u nction regi s ter ( s fr) s p a ce i s s hown in t ab le 4-1 . s ee a l s o ?regi s ter index? on p a ge 153 . note th a t not a ll of the a ddre ss e s a re occ u pied, a nd u nocc u pied a ddre ss e s m a y not b e imple- mented on the chip. re a d a cce ss e s to the s e a ddre ss e s will in gener a l ret u rn r a ndom d a t a , a nd write a cce ss e s will h a ve a n indetermin a te effect. u s er s oftw a re s ho u ld not write to the s e u nli s ted loc a tion s , s ince they m a y b e us ed in f u t u re prod u ct s to invoke new fe a t u re s . note s :1.all s fr s in the left-mo s t col u mn a re b it- a ddre ssab le. 2. re s et v a l u e i s 1111 1111b when tri s t a te-port f us e i s en ab led a nd 0000 0000b when di sab led. table 4-1. at 8 9lp3240/6440 s fr m a p a nd re s et v a l u e s 8 9abcdef 0f 8 h 0ffh 0f0h b 0000 0000 bx 0000 0000 0f7h 0e 8 h s p s r 000x x000 s pcr 0000 0000 s pdr xxxx xxxx 0efh 0e0h acc 0000 0000 ax 0000 0000 d s pr 0000 0000 fird 0000 0000 macl 0000 0000 mach 0000 0000 0e7h 0d 8 h dadc 0000 0000 dadi 0000 0000 dadl 0000 0000 dadh 0000 0000 0dfh 0d0h p s w 0000 0000 t2cca 0000 0000 t2ccl 0000 0000 t2cch 0000 0000 t2ccc 0000 0000 t2ccf 0000 0000 0d7h 0c 8 ht2con 0000 0000 t2mod 0000 0000 rcap2l 0000 000 rcap2h 0000 0000 tl2 0000 000 th2 0000 0000 0cfh 0c0h p4 xx11 1111 p1m0 (2) p1m1 0000 0000 p2m0 (2) p2m1 0000 0000 p3m0 (2) p3m1 0000 0000 0c7h 0b 8 h ip 0000 0000 s aden 0000 0000 p0m0 1111 1111 p0m1 0000 0000 p4m0 (2) p4m1 xx00 0000 0bfh 0b0h p3 1111 1111 ie2 xxxx x000 ip2 xxxx x000 ip2h xxxx x000 iph 0000 0000 0b7h 0a 8 h ie 0000 0000 s addr 0000 0000 twcr 0000 0000 tw s r 0000 0000 twar 0000 0000 twdr 0000 0000 twbr 0000 0000 aref 0000 0000 0afh 0a0h p2 1111 1111 dpcf 0000 00x0 wdtr s t (write-only) wdtcon 0000 x000 0a7h 9 8 h s con 0000 0000 s buf xxxx xxxx gpmod 0000 0000 gpl s 0000 0000 gpien 0000 0000 gpif 0000 0000 s px xxxx 0000 ac s rb 1100 0000 9fh 90h p1 1111 1111 tconb 0010 0100 rl0 0000 0000 rl1 0000 0000 rh0 0000 0000 rh1 0000 0000 memcon 0000 00xx ac s ra 0000 0000 97h 88 h tcon 0000 0000 tmod 0000 0000 tl0 0000 0000 tl1 0000 0000 th0 0000 0000 th1 0000 0000 auxr 0000 0000 clkreg 0000 x000 8 fh 8 0h s p 0000 0111 dp0l 0000 0000 dp0h 0000 0000 dp1l 0000 0000 dp1h 0000 0000 pag e 0000 0000 pcon 0000 0000 8 7h 01234567
23 3706c?micro?2/11 at89lp3240/6440 5. enhanced cpu the at 8 9lp3240/6440 us e s a n enh a nced 8 051 cpu th a t r u n s a t 6 to 12 time s the s peed of s t a nd a rd 8 051 device s (or 3 to 6 time s the s peed of x2 8 051 device s ). the incre as e in perfor- m a nce i s d u e to two f a ctor s . fir s t, the cpu fetche s one in s tr u ction b yte from the code memory every clock cycle. s econd, the cpu us e s a s imple two- s t a ge pipeline to fetch a nd exec u te in s tr u ction s in p a r a llel. thi s bas ic pipelining concept a llow s the cpu to o b t a in u p to 1mip s per mhz. a s imple ex a mple i s s hown in fig u re 5-1 . the 8 051 in s tr u ction s et a llow s for in s tr u ction s of v a ri ab le length from 1 to 3 b yte s . in a s ingle- clock-per- b yte-fetch s y s tem thi s me a n s e a ch in s tr u ction t a ke s a t le as t as m a ny clock s as it h as b yte s to exec u te. the m a jority of in s tr u ction s in the at 8 9lp3240/6440 follow thi s r u le: the in s tr u ction exec u tion time in clock cycle s eq ua l s the n u m b er of b yte s per in s tr u ction, with a few exception s . br a nche s a nd c a ll s req u ire a n a ddition a l cycle to comp u te the t a rget a ddre ss a nd s ome other complex in s tr u ction s req u ire m u ltiple cycle s . s ee ?in s tr u ction s et su mm a ry? on p a ge 143. for more det a iled inform a tion on individ ua l in s tr u ction s . fig u re s 5-2 a nd 5-3 s how ex a mple s of 1- a nd 2- b yte in s tr u ction s . figure 5-1. p a r a llel in s tr u ction fetche s a nd exec u tion s figure 5-2. s ingle-cycle alu oper a tion (ex a mple: inc r0) s y s tem clock n th in s tr u ction (n+1) th in s tr u ction fetch exec u te fetch exec u te fetch t n t n+1 t n+2 (n+2) th in s tr u ction s y s tem clock to t a l exec u tion time regi s ter oper a nd fetch t 1 t 2 t 3 alu oper a tion exec u te re su lt write b a ck fetch next in s tr u ction
24 3706c?micro?2/11 at89lp3240/6440 figure 5-3. two-cycle alu oper a tion (ex a mple: add a, #d a t a ) 5.1 multiply?accumulate unit (mac) the at 8 9lp3240/6440 incl u de s a m u ltiply a nd a cc u m u l a te (mac) u nit th a t c a n s ignific a ntly s peed u p m a ny m a them a tic a l oper a tion s req u ired for digit a l s ign a l proce ss ing. the mac u nit incl u de s a 16- b y-16 b it m u ltiplier a nd a 40- b it a dder th a t c a n perform integer or fr a ction a l m u lti- ply- a cc u m u l a te oper a tion s on s igned 16- b it inp u t v a l u e s . the mac u nit a l s o incl u de s a 1- b it a rithmetic s hifter th a t will left or right s hift the content s of the 40- b it mac a cc u m u l a tor regi s ter (m). a b lock di a gr a m of the mac u nit i s s hown in fig u re 5-4 . the 16- b it s igned oper a nd s a re pro- vided b y the regi s ter p a ir s (ax,acc) a nd (bx,b) where ax (e1h) a nd bx (f7h) hold the higher order b yte s . the 16- b y-16 b it m u ltiplic a tion i s comp u ted thro u gh p a rti a l prod u ct s us ing the at 8 9lp3240/6440? s 8 - b it m u ltiplier. the 32- b it s igned prod u ct i s a dded to the 40- b it m a cc u m u - l a tor regi s ter. the mac oper a tion i s su mm a rized as follow s : all comp u t a tion i s done in s igned two? s complement form. figure 5-4. m u ltiply?acc u m u l a te unit s y s tem clock to t a l exec u tion time fetch immedi a te oper a nd t 1 t 2 t 3 alu oper a tion exec u te re su lt write b a ck fetch next in s tr u ction mac ab: m m ax acc {, } bx b {,} + 3 m4 m2 m1 m0 acc ax bx b 8 x 8-bit signed mult 40-bit add shifter mach macl psw mrw smla smlb
25 3706c?micro?2/11 at89lp3240/6440 the mac oper a tion i s performed b y exec u ting the mac ab (a5 a4h) extended in s tr u ction. thi s two- b yte in s tr u ction req u ire s nine clock cycle s to complete. the oper a nd regi s ter s a re not modi- fied b y the in s tr u ction a nd the re su lt i s s tored in the 40- b it m regi s ter. mac ab a l s o u pd a te s the c a nd ov fl a g s in p s w. c repre s ent s the s ign of the mac re su lt a nd ov i s the two? s comple- ment overflow. note th a t mac ab will not cle a r ov if it w as previo us ly s et to one. three a ddition a l extended in s tr u ction s oper a te directly on the m regi s ter. clr m (a5 e4h) cle a r s the entire 40- b it regi s ter in two clock cycle s . l s l m (a5 23h) a nd a s r (a5 03h) s hift m one b it to the left a nd right re s pectively. right s hift s a re done a rithmetic a lly, i.e. the s ign i s pre s erved. the 40- b it m regi s ter i s a cce ss i b le 16- b it s a t a time thro u gh a s liding window as s hown in fig u re 5-5 . the mrw 1-0 b it s in d s pr ( t ab le 5-1 ) s elect which 16- b it s egment i s c u rrently a cce ss i b le thro u gh the macl a nd mach a ddre ss e s . for norm a l fixed point oper a tion s the window c a n b e fixed to the r a nk of intere s t. for ex a mple, m u ltiplying two 1.15 form a t n u m b er s pl a ce s a 2.30 for- m a t re su lt in the m regi s ter. if mrw i s s et to 10b, a 1.15 v a l u e i s o b t a ined a fter performing a s ingle l s l m. figure 5-5. m regi s ter with s liding window a s a con s eq u ence of the mac u nit, the s t a nd a rd 8 x 8 mul ab in s tr u ction c a n su pport s igned m u ltiplic a tion. the s mla a nd s mlb b it s in d s pr control the m u ltiplier? s interpret a tion of the acc a nd b regi s ter s , a llowing a ny com b in a tion of s igned a nd u n s igned oper a nd m u ltiplic a tion. the s e b it s h a ve no effect on the mac oper a tion which a lw a y s m u ltiplie s s igned- b y- s igned. 5.2 enhanced dual data pointers the at 8 9lp3240/6440 provide s two 16- b it d a t a pointer s : dptr0 formed b y the regi s ter p a ir dpol a nd dpoh ( 8 2h a n 8 3h), a nd dptr1 formed b y the regi s ter p a ir dp1l a nd dp1h ( 8 4h a nd 8 5h). the d a t a pointer s a re us ed b y s ever a l in s tr u ction s to a cce ss the progr a m or d a t a memorie s . the d a t a pointer config u r a tion regi s ter (dpcf) control s oper a tion of the d ua l d a t a pointer s ( t ab le 5-5 on p a ge 2 8 ). the dp s b it in dpcf s elect s which d a t a pointer i s c u rrently ref- erenced b y in s tr u ction s incl u ding the dptr oper a nd. e a ch d a t a pointer m a y b e a cce ss ed a t it s re s pective s fr a ddre ss e s reg a rdle ss of the dp s v a l u e. the at 8 9lp3240/6440 provide s two method s for f as t context s witching of the d a t a pointer s : ? bit 2 of dpcf i s h a rd-wired as a logic 0. the dp s b it m a y b e toggled (to s witch d a t a pointer s ) s imply b y incrementing the dpcf regi s ter, witho u t a ltering other b it s in the regi s ter u nintention a lly. thi s i s the preferred method when only a s ingle d a t a pointer will b e us ed a t one time. ex: inc dpcf ; toggle dps m 2 3 ? 16 15 ? 8 7 ? 0 3 1 ? 24 3 9 ? 3 2 byte 4 byte 3 byte 2 byte 1 byte 0 mach macl mach macl mach macl mach macl mrw 1-0 = 00b mrw 1-0 = 01b mrw 1-0 = 10b mrw 1-0 = 11b
26 3706c?micro?2/11 at89lp3240/6440 ?in s ome c as e s , b oth d a t a pointer s m us t b e us ed s im u lt a neo us ly. to prevent freq u ent toggling of dp s , the at 8 9lp3240/6440 su pport s a prefix not a tion for s electing the oppo s ite d a t a pointer per in s tr u ction. all dptr in s tr u ction s , with the exception of jmp @a+dptr, when prefixed with a n 0a5h opcode will us e the inver s e v a l u e of dp s (dp s ) to s elect the d a t a pointer. s ome ass em b ler s m a y su pport thi s oper a tion b y us ing the /dptr oper a nd. for ex a mple, the following code perform s a b lock copy within edata: mov dpcf, #00h ; dps = 0 mov dptr, #src ; load source address to dptr0 mov /dptr, #dst ; load destination address to dptr1 mov r7, #blksize ; number of bytes to copy copy: movx a, @dptr ; read source (dptr0) inc dptr ; next src (dptr0+1) movx @/dptr, a ; write destination (dptr1) inc /dptr ; next dst (dptr1+1) djnz r7, copy for ass em b ler s th a t do not su pport thi s not a tion, the 0a5h prefix m us t b e decl a red in-line: ex: db 0a5h inc dptr ; equivalent to inc /dptr table 5-1. d s pr ? digit a l s ign a l proce ss ing config u r a tion regi s ter d s pr = e2h re s et v a l u e = 0000 0000b not bit addre ssab le mrw1 mrw0 s mlb s mla cbe1 cbe0 mvcd dprb bit76543210 symbol function mrw 1-0 m regi s ter window. s elect s which p a ir of b yte s from the 5- b yte m regi s ter i s a cce ss i b le thro u gh mach (e5h) a nd macl (e4h) as s hown in fig u re 5-5 . for ex a mple, mrw = 10b for norm a l 16- b it fixed-point oper a tion s where the lowe s t order portion of the fr a ction a l re su lt i s di s c a rded. s mlb s igned m u ltiply oper a nd b. when s mlb = 0, the mul ab in s tr u ction tre a t s the content s of b as a n u n s igned v a l u e. when s mlb = 1, the mul ab in s tr u ction interpret s the content s of b as a s igned two? s complement v a l u e. s mlb doe s not a ffect the mac oper a tion. s mla s igned m u ltiply oper a nd a. when s mla = 0, the mul ab in s tr u ction tre a t s the content s of acc as a n u n s igned v a l u e. when s mla = 1, the mul ab in s tr u ction interpret s the content s of acc as a s igned two? s complement v a l u e. s mla doe s not a ffect the mac oper a tion. cbe1 dptr1 circ u l a r b u ffer en ab le. s et cbe1 = 1 to config u re dptr1 for circ u l a r a ddre ss ing over the two circ u l a r bu ffer a ddre ss r a nge s . cle a r cbe1 for norm a l dptr oper a tion. cbe0 dptr0 circ u l a r b u ffer en ab le. s et cbe0 = 1 to config u re dptr0 for circ u l a r a ddre ss ing over the two circ u l a r bu ffer a ddre ss r a nge s . cle a r cbe0 for norm a l dptr oper a tion. mvcd movc index di sab le. when mvcd = 0, the movc a, @a+dptr in s tr u ction f u nction s norm a lly with indexed a ddre ss ing. s etting mvcd = 1 di sab le s the indexed a ddre ss ing mode su ch th a t movc a, @a+dptr f u nction s as movc a, @dptr. dprb dptr1 redirect to b. dprb s elect s the s o u rce/de s tin a tion regi s ter for movc/movx in s tr u ction s th a t reference dptr1. when dprb = 0, acc i s the s o u rce/de s tin a tion. when dprb = 1, b i s the s o u rce/de s tin a tion. dprb doe s not ch a nge the index regi s ter for movc in s tr u ction s .
27 3706c?micro?2/11 at89lp3240/6440 a su mm a ry of d a t a pointer in s tr u ction s with f as t context s witching i s li s ted in t ab le 5-2 . 5.2.1 data pointer update the d ua l d a t a pointer s on the at 8 9lp3240/6440 incl u de two fe a t u re s th a t control how the d a t a pointer s a re u pd a ted. the d a t a pointer decrement b it s , dpd1 a nd dpd0 in dpcf, config u re the inc dptr in s tr u ction to a ct as dec dptr. the re su lting oper a tion will depend on dp s as s hown in t ab le 5-3 . the d a t a pointer u pd a te b it s , dpu1 a nd dpu0, a llow movx @dptr a nd movc @dptr in s tr u ction s to u pd a te the s elected d a t a pointer au tom a tic a lly in a po s t-increment or po s t-decre- ment f as hion. the direction of u pd a te depend s on the dpd1 a nd dpd0 b it s as s hown in t ab le 5-4 . table 5-2. d a t a pointer in s tr u ction s instruction operation dps = 0 dps = 1 jmp @a+dptr jmp @a+dptr0 jmp @a+dptr1 mov dptr, #d a t a 16 mov dptr0, #d a t a 16 mov dptr1, #d a t a 16 mov /dptr, #d a t a 16 mov dptr1, #d a t a 16 mov dptr0, #d a t a 16 inc dptr inc dptr0 inc dptr1 inc /dptr inc dptr1 inc dptr0 movc a,@a+dptr movc a,@a+dptr0 movc a,@a+dptr1 movc a,@a+/dptr movc a,@a+dptr1 movc a,@a+dptr0 movx a,@dptr movx a,@dptr0 movx a,@dptr1 movx a,@/dptr movx a,@dptr1 movx a,@dptr0 movx @dptr, a movx @dptr0, a movx @dptr1, a movx @/dptr, a movx @dptr1, a movx @dptr0, a table 5-3. d a t a pointer decrement beh a vior dpd1 dpd0 equivalent operation for inc dptr and inc /dptr dps = 0 dps = 1 inc dptr inc /dptr inc dptr inc /dptr 0 0 inc dptr0 inc dptr1 inc dptr1 inc dptr0 0 1 dec dptr0 inc dptr1 inc dptr1 dec dptr0 1 0 inc dptr0 dec dptr1 dec dptr1 inc dptr0 1 1 dec dptr0 dec dptr1 dec dptr1 dec dptr0 table 5-4. d a t a pointer a u to-upd a te dpd1 dpd0 update operation for movx and movc (dpu1 = 1 & dpu0 = 1) dps = 0 dps = 1 dptr /dptr dptr /dptr 0 0 dptr0++ dptr1++ dptr1++ dptr0++ 0 1 dptr0-- dptr1++ dptr1++ dptr0-- 1 0 dptr0++ dptr1-- dptr1-- dptr0++ 1 1 dptr0-- dptr1-- dptr1-- dptr0--
28 3706c?micro?2/11 at89lp3240/6440 5.2.2 data pointer operating modes the d ua l d a t a pointer s on the at 8 9lp3240/6440 incl u de three a ddition a l oper a ting mode s th a t a ffect d a t a pointer bas ed in s tr u ction s . the s e mode s a re controlled b y b it s in d s pr. 5.2.2.1 dptr redirect the d a t a pointer redirect to b b it, dprb (d s pr.0), a llow s movx a nd movc in s tr u ction s to us e the b regi s ter as the d a t a s o u rce/de s tin a tion when the in s tr u ction reference s dptr1 as s hown in t ab le 5-6 a nd t ab le 5-7 . dprb c a n improve the efficiency of ro u tine s th a t m us t fetch m u ltiple oper a nd s from different ram loc a tion s . table 5-5. dpcf ? d a t a pointer config u r a tion regi s ter dpcf = a2h re s et v a l u e = 0000 00x0b not bit addre ssab le dpu1 dpu0 dpd1 dpd0 s igen 0 ? dp s bit76543210 symbol function dpu1 d a t a pointer 1 upd a te. when s et, movx @dptr a nd movc @dptr in s tr u ction s th a t us e dptr1 will a l s o u pd a te dptr1 bas ed on dpd1. if dpd1 = 0 the oper a tion i s po s t-increment a nd if dpd1 = 1 the oper a tion i s po s t-decrement. when dpu1 = 0, dptr1 i s not u pd a ted. dpu0 d a t a pointer 0 upd a te. when s et, movx @dptr a nd movc @dptr in s tr u ction s th a t us e dptr0 will a l s o u pd a te dptr0 bas ed on dpd0. if dpd0 = 0 the oper a tion i s po s t-increment a nd if dpd0 = 1 the oper a tion i s po s t-decrement. when dpu0 = 0, dptr0 i s not u pd a ted. dpd1 d a t a pointer 1 decrement. when s et, inc dptr in s tr u ction s t a rgeted to dptr1 will decrement dptr1. when cle a red, inc dptr in s tr u ction s will increment dptr1. dpd1 a l s o determine s the direction of au to- u pd a te for dptr1 when dpu1 = 1. dpd0 d a t a pointer 0 decrement. when s et, inc dptr in s tr u ction s t a rgeted to dptr0 will decrement dptr0. when cle a red, inc dptr in s tr u ction s will increment dptr0. dpd0 a l s o determine s the direction of au to- u pd a te for dptr0 when dpu0 = 1. s igen s ign a t u re en ab le. when s igen = 1 a ll movc @dptr in s tr u ction s a nd a ll iap a cce ss e s will t a rget the s ign a t u re a rr a y memory. when s igen = 0, a ll movc a nd iap a cce ss e s t a rget code memory. dp s d a t a pointer s elect. dp s s elect s the a ctive d a t a pointer for in s tr u ction s th a t reference dptr. when dp s = 0, dptr will t a rget dptr0 a nd /dptr will t a rget dptr1. when dp s = 1, dptr will t a rget dptr1 a nd /dptr will t a rget dptr0. table 5-6. movx @dptr oper a ting mode s dprb dps equivalent operation for movx movx a, @dptr movx @dptr, a dptr /dptr dptr /dptr 00 movx a, @dptr0 movx a, @dptr1 movx @dptr0, a movx @dptr1, a 01 movx a, @dptr1 movx a, @dptr0 movx @dptr1, a movx @dptr0, a 10 movx a, @dptr0 movx b, @dptr1 movx @dptr0, a movx @dptr1, b 11 movx b, @dptr1 movx a, @dptr0 movx @dptr1, b movx @dptr0, a
29 3706c?micro?2/11 at89lp3240/6440 5.2.2.2 index disable the movc index di sab le b it, mvcd (d s pr.1), di sab le s the indexed a ddre ss ing mode of the movc a, @a+dptr in s tr u ction. when mvcd = 1, the movc in s tr u ction f u nction s as movc a, @dptr with no indexing as s hown in t ab le 5-7 . mvcd c a n improve the efficiency of ro u tine s th a t m us t fetch m u ltiple oper a nd s from progr a m memory. dprb c a n ch a nge the movc de s tin a tion regi s ter from acc to b, bu t h as no effect on the movc index regi s ter. 5.2.2.3 circular buffers the cbe0 a nd cbe1 b it s in d s pr c a n config u re dptr0 a nd dptr1, re s pectively, to oper a te in circ u l a r bu ffer mode. the at 8 9lp3240/6440 m a p s circ u l a r bu ffer s into two identic a lly s ized region s of edata/xdata. the s e bu ffer s c a n s peed u p convol u tion comp u t a tion s su ch as fir a nd iar digit a l filter s . the length of the bu ffer s a re s et b y the v a l u e of the fird (e3h) regi s ter for u p to 256 entrie s . b u ffer a i s m a pped from 0000h to fird a nd b u ffer b i s m a pped from 0100h to 100h+fird as s hown in fig u re 5-6 . both d a t a pointer s m a y oper a te in either bu ffer. when circ u l a r bu ffer mode i s en ab led, u pd a te s to a d a t a pointer referencing the bu ffer region will follow circ u l a r a ddre ss ing r u le s . if the d a t a pointer i s eq ua l to fird or 100h+fird a ny incre- ment will c aus e it to overflow to 0000h or 0100h re s pectively. if the d a t a pointer i s eq ua l to 0000h or 0100h a ny decrement will c aus e it to u nderflow to fird or 100h+fird re s pectively. in thi s mode, u pd a te s c a n b e either a n explicit inc dptr or a n au tom a tic u pd a te us ing dpu n where the dpd n b it s control the direction. the d a t a pointer will increment or decrement norm a lly a t a ny other a ddre ss e s . therefore, when circ u l a r a ddre ss ing i s in us e, the d a t a pointer s c a n s till oper a te as reg u l a r pointer s in the fird+1 to 00ffh a nd gre a ter th a n 100h+fird r a nge s . figure 5-6. circ u l a r b u ffer mode table 5-7. movc @dptr oper a ting mode s mvcd dprb equivalent operation for movc a, @a+dptr dps = 0 dps = 1 dptr /dptr dptr /dptr 00 movc a, @a+dptr0 movc a, @a+dptr1 movc a, @a+dptr1 movc a, @a+dptr0 01 movc a, @a+dptr0 movc b, @a+dptr1 movc b, @a+dptr1 movc a, @a+dptr0 10 movc a, @dptr0 movc a, @dptr1 movc a, @dptr1 movc a, @dptr0 11 movc a, @dptr0 movc b, @dptr1 movc b, @dptr1 movc a, @dptr0 0000h dptr 0100h fird 100h + fird dptr dpdn = 0 dpdn = 1 dpdn = 0 dpdn = 1 a b
30 3706c?micro?2/11 at89lp3240/6440 5.3 instruction set extensions t ab le 5- 8 li s t s the a ddition s to the 8 051 in s tr u ction s et th a t a re su pported b y the at 8 9lp3240/6440. for more inform a tion on the in s tr u ction s et s ee s ection 22. ?in s tr u ction s et su mm a ry? on p a ge 143 . for det a iled de s cription s of the extended in s tr u ction s s ee s ection 22.1 ?in s tr u ction s et exten s ion s ? on p a ge 147 . ? the /dptr in s tr u ction s provide su pport for the d ua l d a t a pointer fe a t u re s de s cri b ed ab ove ( s ee s ection 5.2 ). ?the a s r m, l s l m, clr m a nd mac ab in s tr u ction s a re p a rt of the m u ltiply-acc u m u l a te unit ( s ee s ection 5.1 ). ?the jmp @a+pc in s tr u ction su pport s loc a lized j u mp t ab le s witho u t us ing a d a t a pointer. ?the cjne a, @r i , rel in s tr u ction s a llow comp a re s of a rr a y v a l u e s with non-con s t a nt v a l u e s . ? the break in s tr u ction i s us ed b y the on-chip de bu g s y s tem. s ee s ection 24. on p a ge 155 . table 5-8. at 8 9lp3240/6440 extended in s tr u ction s opcode mnemonic description bytes cycles a5 00 break s oftw a re b re a kpoint 2 2 a5 03 a s r m arithmetic s hift right of m regi s ter 2 2 a5 23 l s l m logic a l s hift left of m regi s ter 2 2 a5 73 jmp @a+pc indirect j u mp rel a tive to pc 2 3 a5 90 mov /dptr, #d a t a 16 move 16- b it con s t a nt to a ltern a te d a t a pointer 44 a5 93 movc a, @a+/dptr move code loc a tion to acc rel a tive to a ltern a te d a t a pointer 24 a5 a3 inc /dptr increment a ltern a te d a t a pointer 2 3 a5 a4 mac ab m u ltiply a nd a cc u m u l a te 2 9 a5 b6 cjne a, @r0, rel comp a re acc to indirect ram a nd j u mp if not eq ua l 34 a5 b7 cjne a, @r1, rel comp a re acc to indirect ram a nd j u mp if not eq ua l 34 a5 e0 movx a, @/dptr move extern a l to acc; 16- b it a ddre ss in a ltern a te d a t a pointer 23/5 a5 e4 clr m cle a r m regi s ter 2 2 a5 f0 movx @/dptr, a move acc to extern a l; 16- b it a ddre ss in a ltern a te d a t a pointer 23/5
31 3706c?micro?2/11 at89lp3240/6440 6. system clock the s y s tem clock i s gener a ted directly from one of three s elect ab le clock s o u rce s . the three s o u rce s a re the on-chip cry s t a l o s cill a tor, extern a l clock s o u rce, a nd intern a l rc o s cill a tor. the on-chip cry s t a l o s cill a tor m a y a l s o b e config u red for low or high s peed oper a tion. the clock s o u rce i s s elected b y the clock s o u rce u s er f us e s as s hown in t ab le 6-1 . s ee ?u s er config u r a - tion f us e s ? on p a ge 164 . by def au lt, no intern a l clock divi s ion i s us ed to gener a te the cpu clock from the s y s tem clock. however, the s y s tem clock divider m a y b e us ed to pre s c a le the s y s tem clock. the choice of clock s o u rce a l s o a ffect s the s t a rt- u p time a fter a por, bod or power- down event ( s ee ?re s et? on p a ge 33 or ?power-down mode? on p a ge 37 ) 6.1 crystal oscillator when en ab led, the intern a l inverting o s cill a tor a mplifier i s connected b etween xtal1 a nd xtal2 for connection to a n extern a l q ua rtz cry s t a l or cer a mic re s on a tor. the o s cill a tor m a y oper a te in either high- s peed or low- s peed mode. low- s peed mode i s intended for 32.76 8 khz w a tch cry s t a l s a nd con su me s le ss power th a n high- s peed mode. the config u r a tion as s hown in fig u re 6-1 a pplie s for b oth high a nd low s peed o s cill a tor s . note th a t the intern a l s tr u ct u re of the device a dd s ab o u t 10 pf of c a p a cit a nce to b oth xtal1 a nd xtal2, s o th a t in s ome c as e s le ss extern a l c a p a cit a nce m a y b e req u ired. the tot a l c a p a cit a nce on xtal1 or xtal2, incl u ding the extern a l lo a d c a p a citor pl us intern a l device lo a d, b o a rd tr a ce a nd cry s t a l lo a ding s , s ho u ld not exceed 20 pf. an option a l re s i s tor r1 c a n b e connected to xtal1 in pl a ce of c1 for improved s t a rt u p perform a nce with higher s peed cry s t a l s . when us ing the cry s t a l o s cill a tor, p4.0 a nd p4.1 will h a ve their inp u t s a nd o u tp u t s di sab led. al s o, xtal2 in cry s t a l o s cill a tor mode s ho u ld not b e us ed to directly drive a b o a rd-level clock witho u t a bu ffer. figure 6-1. cry s t a l o s cill a tor connection s note: 1. c1/c2 = 5?15 pf for cry s t a l s = 5?15 pf for cer a mic re s on a tor s r1 = 4?5 m table 6-1. clock s o u rce s etting s clock source fuse 1 clock source fuse 0 selected clock source 0 0 high s peed cry s t a l o s cill a tor (f > 500 khz) 01low s peed cry s t a l o s cill a tor (f 100 khz) 10extern a l clock on xtal1 1 1 intern a l 8 mhz rc o s cill a tor ~10 pf ~10 pf c2 r1 c1 optional
32 3706c?micro?2/11 at89lp3240/6440 6.2 external clock source the extern a l clock option di sab le s the o s cill a tor a mplifier a nd a llow s xtal1 to b e driven directly b y a n extern a l clock s o u rce as s hown in fig u re 6-2 . xtal2 m a y b e left u nconnected, us ed as gener a l p u rpo s e i/o p4.1, or config u red to o u tp u t a divided ver s ion of the s y s tem clock. figure 6-2. extern a l clock drive config u r a tion 6.3 internal rc oscillator the at 8 9lp3240/6440 h as a n intern a l rc o s cill a tor (irc) t u ned to 8 .0 mhz 2.5%. when en ab led as the clock s o u rce, xtal1 a nd xtal2 m a y b e us ed as p4.0 a nd p4.1 re s pectively. xtal2 m a y a l s o b e config u red to o u tp u t a divided ver s ion of the s y s tem clock. the freq u ency of the o s cill a tor m a y b e a dj us ted within limit s b y ch a nging the rc c a li b r a tion byte s tored a t b yte 12 8 of the u s er s ign a t u re arr a y. thi s loc a tion m a y b e u pd a ted us ing the iap interf a ce (loc a tion 01 8 0h in s ig s p a ce) or b y a n extern a l device progr a mmer (urow loc a tion 00 8 0h). s ee s ec- tion 25. 8 ?u s er s ign a t u re a nd an a log config u r a tion? on p a ge 165 . a copy of the f a ctory c a li b r a tion b yte i s s tored a t b yte 8 of the atmel s ign a t u re arr a y (000 8 h in s ig s p a ce). 6.4 system clock out when the at 8 9lp3240/6440 i s config u red to us e either a n extern a l clock or the intern a l rc o s cill a tor, the s y s tem clock divided b y 2 m a y b e o u tp u t on xtal2 (p4.1). the clock o u t fe a t u re i s en ab led b y s etting the coe b it in clkreg. for ex a mple, s etting coe = ?1? when us ing the intern a l o s cill a tor will re su lt in a 4.0 mhz (2.5%) clock o u tp u t on p4.1. p4.1 m us t b e config u red as a n o u tp u t in order to us e the clock o u t fe a t u re. 6.5 system clock divider the cdv 2-0 b it s in clkreg a llow the s y s tem clock to b e divided down from the s elected clock s o u rce b y power s of 2. the clock divider provide s us er s with a gre a ter freq u ency r a nge when us ing the intern a l rc o s cill a tor. for ex a mple, to a chieve a 1 mhz s y s tem freq u ency when us ing the irc, cdv 2-0 s ho u ld b e s et to 011b for divide- b y- 8 oper a tion. the divider c a n a l s o b e us ed to red u ce power con su mption b y decre as ing the oper a tion a l freq u ency d u ring non-critic a l period s . the re su lting s y s tem freq u ency i s given b y the following eq ua tion: where f o s c i s the freq u ency of the s elected clock s o u rce. the clock divider will pre s c a le the clock for the cpu a nd a ll peripher a l s . the v a l u e of cdv m a y b e ch a nged a t a ny time witho u t interr u pt- ing norm a l exec u tion. ch a nge s to cdv a re s ynchronized su ch th a t the s y s tem clock will not xtal2 (p4.1) xtal1 (p4.0) gnd nc, gpio, or clkout external oscillator signal f s y s f o s c 2 cdv ------------ - =
33 3706c?micro?2/11 at89lp3240/6440 p ass thro u gh intermedi a te freq u encie s . when cdv i s u pd a ted, the new freq u ency will t a ke a ffect within a m a xim u m period of 12 8 x t o s c . 7. reset d u ring re s et, a ll i/o regi s ter s a re s et to their initi a l v a l u e s , the port pin s a re tri s t a ted, a nd the progr a m s t a rt s exec u tion from the re s et vector, 0000h. the at 8 9lp3240/6440 h as five s o u rce s of re s et: power-on re s et, b rown-o u t re s et, extern a l re s et, w a tchdog re s et, a nd s oftw a re re s et. 7.1 power-on reset a power-on re s et (por) i s gener a ted b y a n on-chip detection circ u it. the detection level v por i s nomin a lly 1.4v. the por i s a ctiv a ted whenever v dd i s b elow the detection level. the por cir- c u it c a n b e us ed to trigger the s t a rt- u p re s et or to detect a su pply volt a ge f a il u re in device s witho u t a b rown-o u t detector. the por circ u it en su re s th a t the device i s re s et from power-on. a power-on s eq u ence i s s hown in fig u re 7-1 on p a ge 34 . when v dd re a che s the power-on re s et thre s hold volt a ge v por , a n initi a liz a tion s eq u ence l as ting t por i s s t a rted. when the initi a liz a tion s eq u ence complete s , the s t a rt- u p timer determine s how long the device i s kept in por a fter v dd ri s e. the por s ign a l i s a ctiv a ted a g a in, witho u t a ny del a y, when v dd f a ll s b elow the por thre s hold level. a power-on re s et (i.e. a cold re s et) will s et the pof fl a g in pcon. the intern a lly table 6-2. clkreg ? clock control regi s ter clkreg = 8 fh re s et v a l u e = 0000 0000b not bit addre ssab le tp s 3tp s 2tp s 1tp s 0 cdv2 cdv1 cdv0 coe bit76543210 symbol function tp s [3-0] timer pre s c a ler. the timer pre s c a ler s elect s the time bas e for timer 0, timer 1, timer 2 a nd the w a tchdog timer. the pre s c a ler i s implemented as a 4- b it b in a ry down co u nter. when the co u nter re a che s zero it i s relo a ded with the v a l u e s tored in the tp s b it s to give a divi s ion r a tio b etween 1 a nd 16. by def au lt the timer s will co u nt every clock cycle (tp s = 0000b). to config u re the timer s to co u nt a t a s t a nd a rd 8 051 r a te of once every 12 clock cycle s , tp s s ho u ld b e s et to 1011b. cdv[2-0] s y s tem clock divi s ion. determine s the freq u ency of the s y s tem clock rel a tive to the o s cill a tor clock s o u rce. cdiv2 cdiv1 cdiv0 s y s tem clock freq u ency 000f o s c /1 001f o s c /2 010f o s c /4 011f o s c / 8 100f o s c /16 101f o s c /32 110f o s c /64 111f o s c /12 8 coe clock o u t en ab le. s et coe to o u tp u t the s y s tem clock divided b y 2 on xtal2 (p4.1). the intern a l rc o s cill a tor or extern a l clock s o u rce m us t b e s elected in order to us e thi s fe a t u re a nd p4.1 m us t b e config u red as a n o u tp u t.
34 3706c?micro?2/11 at89lp3240/6440 gener a ted re s et c a n b e extended b eyond the power-on period b y holding the r s t pin low longer th a n the time-o u t. figure 7-1. power-on re s et s eq u ence (bod di sab led) if the brown-o u t detector (bod) i s a l s o en ab led, the s t a rt- u p timer doe s not b egin co u nting u ntil a fter v dd re a che s the bod thre s hold volt a ge v bod as s hown in fig u re 7-2 . however, if thi s event occ u r s prior to the end of the initi a liz a tion s eq u ence, the timer m us t fir s t w a it for th a t s eq u ence to complete b efore co u nting. figure 7-2. power-on re s et s eq u ence (bod en ab led) note: t por i s a pproxim a tely 143 s 5%. the s t a rt- u p timer del a y i s us er-config u r ab le with the s t a rt- u p time u s er f us e s a nd depend s on the clock s o u rce ( t ab le 7-1 ). the s t a rt-up time f us e s a l s o control the length of the s t a rt- u p time a fter a brown-o u t re s et or when w a king u p from power-down d u ring intern a lly timed mode. the s t a rt- u p del a y s ho u ld b e s elected to provide eno u gh s ettling time for v dd a nd the s elected clock s o u rce. the device oper a ting environment ( su pply volt a ge, freq u ency, temper a t u re, etc.) m us t v dd r s t time-o u t t por + t s ut t rhd v por intern a l re s et r s t intern a l re s et v ih (r s t tied to v cc ) (r s t controlled extern a lly) v por v dd r s t time-o u t t por t rhd v por intern a l re s et r s t intern a l re s et v ih t s ut v bod (r s t tied to v cc ) (r s t controlled extern a lly)
35 3706c?micro?2/11 at89lp3240/6440 meet the minim u m s y s tem req u irement s b efore the device exit s re s et a nd s t a rt s norm a l oper a - tion. the r s t pin m a y b e held low extern a lly u ntil the s e condition s a re met. 7.2 brown-out reset the at 8 9lp3240/6440 h as a n on-chip brown-o u t detection (bod) circ u it for monitoring the v dd level d u ring oper a tion b y comp a ring it to a fixed trigger level. the trigger level v bod for the bod i s nomin a lly 2.0v. the p u rpo s e of the bod i s to en su re th a t if v dd f a il s or dip s while exec u ting a t s peed, the s y s tem will gr a cef u lly enter re s et witho u t the po ss i b ility of error s ind u ced b y incorrect exec u tion. a bod s eq u ence i s s hown in fig u re 7-3 . when v dd decre as e s to a v a l u e b elow the trigger level v bod , the intern a l re s et i s immedi a tely a ctiv a ted. when v dd incre as e s ab ove the trigger level pl us ab o u t 200 mv of hy s tere s i s , the s t a rt- u p timer rele as e s the intern a l re s et a fter the s pecified time-o u t period h as expired ( t ab le 7-1 ). the brown-o u t detector m us t b e en ab led b y s etting the bod en ab le f us e. ( s ee ?u s er config u r a tion f us e s ? on p a ge 164. ) figure 7-3. brown-o u t detector re s et the at 8 9lp3240/6440 a llow s for a wide v dd oper a ting r a nge. the on-chip bod m a y not b e su f- ficient to prevent incorrect exec u tion if v bod i s lower th a n the minim u m req u ired v dd r a nge, su ch as when a 3.6v su pply i s co u pled with high freq u ency oper a tion. in su ch c as e s a n extern a l brown-o u t re s et circ u it connected to the r s t pin m a y b e req u ired. 7.3 external reset the p4.2/r s t pin c a n f u nction as either a n a ctive- low re s et inp u t or as a digit a l gener a l- p u rpo s e i/o, p4.2. the re s et pin en ab le f us e, when s et to ?1?, en ab le s the extern a l re s et inp u t f u nction on p4.2. ( s ee ?u s er config u r a tion f us e s ? on p a ge 164. ) when cle a red, p4.2 m a y b e us ed as a n inp u t or o u tp u t pin. when config u red as a re s et inp u t, the pin m us t b e held low for a t le as t two clock cycle s to trigger the intern a l re s et. the r s t pin incl u de s a n on-chip p u ll- u p re s i s - tor tied to v dd . the p u ll- u p i s di sab led when the pin i s config u red as p4.2. table 7-1. s t a rt- u p timer s etting s sut fuse 1 sut fuse 0 clock source t sut ( 5%) s 00 intern a l rc/extern a l clock 16 cry s t a l o s cill a tor 1024 01 intern a l rc/extern a l clock 512 cry s t a l o s cill a tor 204 8 10 intern a l rc/extern a l clock 1024 cry s t a l o s cill a tor 4096 11 intern a l rc/extern a l clock 4096 cry s t a l o s cill a tor 163 8 4 v dd time-o u t v por intern a l re s et t s ut v bod
36 3706c?micro?2/11 at89lp3240/6440 note: d u ring a power- u p s eq u ence, the f us e s election i s a lw a y s overridden a nd therefore the pin will a lw a y s f u nction as a re s et inp u t. an external circuit connected to this pin should not hold this pin low during a power-on sequence if the pin will be configured as a general i/o, as this will keep the device in reset until the pin transitions high . after the power- u p del a y, thi s inp u t will f u nction either as a n extern a l re s et inp u t or as a digit a l inp u t as defined b y the f us e b it. only a power- u p re s et will tempor a rily override the s election defined b y the re s et f us e b it. other s o u rce s of re s et will not override the re s et f us e b it. p4.2/r s t a l s o s erve s as the in- s y s tem progr a mming (i s p) en ab le. i s p i s en ab led when the extern a l re s et pin i s held low. when the re s et pin i s di s - ab led b y the f us e, i s p m a y only b e entered b y p u lling p4.2 low d u ring power- u p. 7.4 watchdog reset when the w a tchdog time s o u t, it will gener a te a n intern a l re s et p u l s e l as ting 16 clock cycle s . w a tchdog re s et will a l s o s et the wdtovf fl a g in wdtcon. to prevent a w a tchdog re s et, the w a tchdog re s et s eq u ence 1eh/e1h m us t b e written to wdtr s t b efore the w a tchdog time s o u t. s ee ?progr a mm ab le w a tchdog timer? on p a ge 141. for det a il s on the oper a tion of the w a tchdog. 7.5 software reset the cpu m a y gener a te a n intern a l 16-clock cycle re s et p u l s e b y writing the s oftw a re re s et s eq u ence 5ah/a5h to the wdr s t regi s ter. a s oftw a re re s et will s et the s wr s t b it in wdt- con. s ee ? s oftw a re re s et? on p a ge 142 for more inform a tion on s oftw a re re s et. writing a ny s eq u ence s other th a n 5ah/a5h or 1eh/e1h to wdtr s t will gener a te a n immedi a te re s et a nd s et b oth wdtovf a nd s wr s t to fl a g a n error. 8. power saving modes the at 8 9lp3240/6440 su pport s two different power-red u cing mode s : idle a nd power-down. the s e mode s a re a cce ss ed thro u gh the pcon regi s ter. addition a l s tep s m a y b e req u ired to a chieve the lowe s t po ss i b le power con su mption while us ing the s e mode s . 8.1 idle mode s etting the idl b it in pcon enter s idle mode. idle mode h a lt s the intern a l cpu clock. the cpu s t a te i s pre s erved in it s entirety, incl u ding the ram, s t a ck pointer, progr a m co u nter, progr a m s t a t us word, a nd a cc u m u l a tor. the port pin s hold the logic s t a te s they h a d a t the time th a t idle w as a ctiv a ted. idle mode le a ve s the peripher a l s r u nning in order to a llow them to w a ke u p the cpu when a n interr u pt i s gener a ted. the timer s , uart, s pi, twi, comp a r a tor s , adc, gpi a nd cca peripher a l s contin u e to f u nction d u ring idle. if the s e f u nction s a re not needed d u ring idle, they s ho u ld b e explicitly di sab led b y cle a ring the a ppropri a te control b it s in their re s pective s fr s . the w a tchdog m a y b e s electively en ab led or di sab led d u ring idle b y s etting/cle a ring the wdidle b it. the brown-o u t detector, if en ab led, i s a lw a y s a ctive d u ring idle. any en ab led inter- r u pt s o u rce or re s et m a y termin a te idle mode. when exiting idle mode with a n interr u pt, the interr u pt will immedi a tely b e s erviced, a nd following reti the next in s tr u ction to b e exec u ted will b e the one following the in s tr u ction th a t p u t the device into idle. the power con su mption d u ring idle mode c a n b e f u rther red u ced b y pre s c a ling down the s y s tem clock us ing the s y s tem clock divider ( s ection 6.5 on p a ge 32 ). be a w a re th a t the clock divider will a ffect a ll peripher a l f u nction s except the adc. therefore bau d r a te s or pwm period s m a y need to b e a dj us ted to m a int a in their r a te with the new clock freq u ency.
37 3706c?micro?2/11 at89lp3240/6440 . 8.2 power-down mode s etting the power-down (pd) b it in pcon enter s power-down mode. power-down mode s top s the o s cill a tor, di sab le s the bod a nd power s down the fl as h memory in order to minimize power con su mption. only the power-on circ u itry will contin u e to dr a w power d u ring power-down. d u r- ing power-down, the power su pply volt a ge m a y b e red u ced to the ram keep- a live volt a ge. the ram content s will b e ret a ined, bu t the s fr content s a re not g ua r a nteed once v dd h as b een red u ced. power-down m a y b e exited b y extern a l re s et, power-on re s et, or cert a in en ab led interr u pt s . 8.2.1 interrupt recovery from power-down three extern a l interr u pt s o u rce s m a y b e config u red to termin a te power-down mode: extern a l interr u pt s int0 (p3.2) a nd int1 (p3.3); a nd the gener a l-p u rpo s e interr u pt s (gpi). to w a ke u p b y extern a l interr u pt int0 or int1 , th a t interr u pt m us t b e en ab led b y s etting ex0 or ex1 in ie a nd m us t b e config u red for level- s en s itive oper a tion b y cle a ring it0 or it1. any gener a l-p u rpo s e interr u pt on port 1 (gpi 7-0 ) c a n a l s o w a ke u p the device. the gpi pin m us t b e en ab led in gpien a nd config u red for level- s en s itive detection, a nd egp in ie2 m us t b e s et in order to termin a te power-down. when termin a ting power-down b y a n interr u pt, two different w a ke- u p mode s a re a v a il ab le. when pwdex in pcon i s zero, the w a ke- u p period i s intern a lly timed as s hown in fig u re 8 -1 . at the f a lling edge on the interr u pt pin, power-down i s exited, the o s cill a tor i s re s t a rted, a nd a n intern a l timer b egin s co u nting. the intern a l clock will not b e a llowed to prop a g a te to the cpu u ntil a fter the timer h as timed o u t. after the time-o u t period the interr u pt s ervice ro u tine will b egin. the time-o u t period i s controlled b y the s t a rt- u p timer f us e s ( s ee t ab le 7-1 on p a ge 35 ). the interr u pt pin need not rem a in low for the entire time-o u t period. table 8-1. pcon ? power control regi s ter pcon = 8 7h re s et v a l u e = 000x 0000b not bit addre ssab le s mod1 s mod0 pwdex pof gf1 gf0 pd idl bit76543210 symbol function s mod1 do ub le b au d r a te b it. do ub le s the bau d r a te of the uart in mode s 1, 2, or 3. s mod0 fr a me error s elect. when s mod0 = 1, s con.7 i s s m0. when s mod0 = 1, s con.7 i s fe. note th a t fe will b e s et a fter a fr a me error reg a rdle ss of the s t a te of s mod0. pwdex power-down exit mo de. when pwdex = 1, w a ke u p from power-down i s extern a lly controlled. when pwdex = 1, w a ke u p from power-down i s intern a lly timed. pof power off fl a g. pof i s s et to ?1? d u ring power u p (i.e. cold re s et). it c a n b e s et or re s et u nder s oftw a re control a nd i s not a ffected b y r s t or bod (i.e. w a rm re s et s ). gf1, gf0 gener a l-p u rpo s e fl a g s pd power-down b it. s etting thi s b it a ctiv a te s power-down oper a tion. the pd b it i s cle a red au tom a tic a lly b y h a rdw a re when w a king u p from power-down. idl idle mode b it. s etting thi s b it a ctiv a te s idle mode oper a tion. the idl b it i s cle a red au tom a tic a lly b y h a rdw a re when w a king u p from idle
38 3706c?micro?2/11 at89lp3240/6440 figure 8-1. interr u pt recovery from power-down (pwdex = 0) when pwdex = ?1?, the w a ke- u p period i s controlled extern a lly b y the interr u pt. ag a in, a t the f a lling edge on the interr u pt pin, power-down i s exited a nd the o s cill a tor i s re s t a rted. however, the intern a l clock will not prop a g a te u ntil the ri s ing edge of the interr u pt pin as s hown in fig u re 8 - 2 . the interr u pt pin s ho u ld b e held low long eno u gh for the s elected clock s o u rce to s t ab ilize. after the ri s ing edge on the pin the interr u pt s ervice ro u tine will b e exec u ted. figure 8-2. interr u pt recovery from power-down (pwdex = 1) 8.2.2 reset recovery from power-down the w a ke- u p from power-down thro u gh a n extern a l re s et i s s imil a r to the interr u pt with pwdex = ?0?. at the f a lling edge of r s t , power-down i s exited, the o s cill a tor i s re s t a rted, a nd a n intern a l timer b egin s co u nting as s hown in fig u re 8 -3 . the intern a l clock will not b e a llowed to prop a g a te to the cpu u ntil a fter the timer h as timed o u t. the time-o u t period i s controlled b y the s t a rt- u p timer f us e s . ( s ee t ab le 7-1 on p a ge 35 ). if r s t ret u rn s high b efore the time-o u t, a two clock cycle intern a l re s et i s gener a ted when the intern a l clock re s t a rt s . otherwi s e, the device will rem a in in re s et u ntil r s t i s b ro u ght high. 8.3 reducing power consumption s ever a l po ss i b ilitie s need con s ider a tion when trying to red u ce the power con su mption in a n at 8 9lp- bas ed s y s tem. gener a lly, idle or po wer-down mode s ho u ld b e us ed as m u ch as po ss i- b le. all u nneeded f u nction s s ho u ld b e di sab led. in p a rtic u l a r, the following mod u le s m a y need s peci a l con s ider a tion when trying to a chieve the lowe s t po ss i b le power con su mption. 8.3.1 brown-out detector if the brown-o u t detector i s not needed b y the a pplic a tion, thi s mod u le s ho u ld b e t u rned off. if the brown-o u t detector i s en ab led b y the bod en ab le f us e, it will b e en ab led in a ll mode s except power-down. s ee s ection 25.7 ?u s er config u r a tion f us e s ? on p a ge 164 . pwd int1 xtal1 t s ut intern a l clock pwd int1 xtal1 intern a l clock
39 3706c?micro?2/11 at89lp3240/6440 figure 8-3. re s et recovery from power-down 8.3.2 analog comparators the comp a r a tor s will oper a te d u ring idle mode if en ab led. to sa ve power, the comp a r a tor s s ho u ld b e di sab led b efore entering idle mode if po ss i b le. when the comp a r a tor s a re t u rned off a nd on a g a in, s ome s ettling time i s req u ired for the a n a log circ u it s to s t ab ilize. if the comp a r a tor s a re en ab led, they will con su me the le as t power when us ing a n extern a l reference, rfa 1-0 =00b a nd rfb 1-0 =00b. 8.3.3 analog-to-digital converter the dadc will oper a te d u ring idle mode if en ab led. to sa ve power, the dadc s ho u ld b e di s - ab led b efore entering idle mode if po ss i b le. when the dadc i s t u rned off a nd on a g a in, s ome s ettling time i s req u ired for the a n a log circ u it s to s t ab ilize. if the dadc i s en ab led, it will con- su me the le as t power when config u red to us e the s y s tem clock in s te a d of the intern a l rc o s cill a tor ( u nle ss the irc i s the s y s tem clock s o u rce) a nd when the intern a l reference i s di sab led (iref = 0). the dadc m us t a lw a y s b e di sab led b efore entering power-down. 9. interrupts the at 8 9lp3240/6440 provide s 12 interr u pt s o u rce s : two extern a l interr u pt s , three timer inter- r u pt s , a s eri a l port interr u pt, a n a n a log comp a r a tor interr u pt, a gener a l-p u rpo s e interr u pt, a comp a re/c a pt u re interr u pt, a two-wire interr u pt, a n adc interr u pt a nd a n s pi interr u pt. the s e interr u pt s a nd the s y s tem re s et e a ch h a ve a s ep a r a te progr a m vector a t the s t a rt of the progr a m memory s p a ce. e a ch interr u pt s o u rce c a n b e individ ua lly en ab led or di sab led b y s etting or cle a r- ing a b it in the interr u pt en ab le regi s ter s ie a nd ie2. the ie regi s ter a l s o cont a in s a glo ba l di sab le b it, ea, which di sab le s a ll interr u pt s . e a ch interr u pt s o u rce c a n b e individ ua lly progr a mmed to one of fo u r priority level s b y s etting or cle a ring b it s in the interr u pt priority regi s ter s ip, iph, ip2 a nd ip2h. ip a nd ip2 hold the low order priority b it s a nd iph a nd ip2h hold the high priority b it s for e a ch interr u pt. an interr u pt s ervice ro u tine in progre ss c a n b e interr u pted b y a higher priority interr u pt, bu t not b y a nother interr u pt of the sa me or lower priority. the highe s t priority interr u pt c a nnot b e interr u pted b y a ny other inter- r u pt s o u rce. if two req u e s t s of different priority level s a re pending a t the end of a n in s tr u ction, the req u e s t of higher priority level i s s erviced. if req u e s t s of the sa me priority level a re pending a t the end of a n in s tr u ction, a n intern a l polling s eq u ence determine s which req u e s t i s s erviced. the polling s eq u ence i s bas ed on the vector a ddre ss ; a n interr u pt with a lower vector a ddre ss h as higher priority th a n a n interr u pt with a higher vector a ddre ss . note th a t the polling s eq u ence i s only us ed to re s olve pending req u e s t s of the sa me priority level. pwd r s t xtal1 t s ut intern a l clock intern a l re s et
40 3706c?micro?2/11 at89lp3240/6440 the ip x d b it s loc a ted a t the s eventh b it of ip, iph, ip2 a nd ip2h c a n b e us ed to di sab le a ll inter- r u pt s of a given priority level, a llowing s oftw a re implement a tion s of more complex interr u pt priority h a ndling s cheme s su ch as level- bas ed ro u nd-ro b in s ched u ling. the extern a l interr u pt s int0 a nd int1 c a n e a ch b e either level- a ctiv a ted or edge- a ctiv a ted, depending on b it s it0 a nd it1 in regi s ter tcon. the fl a g s th a t a ct ua lly gener a te the s e inter- r u pt s a re the ie0 a nd ie1 b it s in tcon. when the s ervice ro u tine i s vectored to, h a rdw a re cle a r s the fl a g th a t gener a ted a n extern a l interr u pt only if the interr u pt w as edge- a ctiv a ted. if the inter- r u pt w as level a ctiv a ted, then the extern a l req u e s ting s o u rce (r a ther th a n the on-chip h a rdw a re) control s the req u e s t fl a g. the timer 0 a nd timer 1 interr u pt s a re gener a ted b y tf0 a nd tf1, which a re s et b y a rollover in their re s pective timer/co u nter regi s ter s (except for timer 0 in mode 3). when a timer interr u pt i s gener a ted, the on-chip h a rdw a re cle a r s the fl a g th a t gener a ted it when the s ervice ro u tine i s vectored to. the timer 2 interr u pt i s gener a ted b y a logic or of b it s tf2 a nd exf2 in regi s ter t2con. neither of the s e fl a g s i s cle a red b y h a rdw a re when the cpu vector s to the s ervice ro u - tine. the s ervice ro u tine norm a lly m us t determine whether tf2 or exf2 gener a ted the interr u pt a nd th a t b it m us t b e cle a red b y s oftw a re. the s eri a l port interr u pt i s gener a ted b y the logic or of ri a nd ti in s con. neither of the s e fl a g s i s cle a red b y h a rdw a re when the cpu vector s to the s ervice ro u tine. the s ervice ro u tine norm a lly m us t determine whether ri or ti gener a ted the interr u pt a nd th a t b it m us t b e cle a red b y s oftw a re. the s eri a l peripher a l interf a ce interr u pt i s gener a ted b y the logic or of s pif, modf a nd txe in s p s r. none of the s e fl a g s i s cle a red b y h a rdw a re when the cpu vector s to the s ervice ro u - tine. the s ervice ro u tine norm a lly m us t determine which b it gener a ted the interr u pt a nd th a t b it m us t b e cle a red b y s oftw a re. a logic or of a ll eight fl a g s in the gpif regi s ter c aus e s the gener a l-p u rpo s e interr u pt. none of the s e fl a g s i s cle a red b y h a rdw a re when the s ervice ro u tine i s vectored to. the s ervice ro u tine m us t determine which b it gener a ted the interr u pt a nd th a t b it m us t b e cle a red in s oftw a re. if the interr u pt w as level a ctiv a ted, then the extern a l req u e s ting s o u rce m us t de- ass ert the interr u pt b efore the fl a g m a y b e cle a red b y s oftw a re. the cfa a nd cfb b it s in ac s ra a nd ac s rb re s pectively gener a te the comp a r a tor interr u pt. the s ervice ro u tine m us t norm a lly determine whether cfa or cfb gener a ted the interr u pt, a nd the b it m us t b e cle a red b y s oftw a re. the dac/adc conver s ion interr u pt i s gener a ted b y adif in dadc. on-chip h a rdw a re cle a r s the adif fl a g when vectoring to the s ervice ro u tine. a logic or of the fo u r le as t s ignific a nt b it s in the t2ccf regi s ter c aus e s the comp a re/c a pt u re arr a y interr u pt. none of the s e fl a g s i s cle a red b y h a rdw a re when the s ervice ro u tine i s vectored to. the s ervice ro u tine m us t determine which b it gener a ted the interr u pt a nd th a t b it m us t b e cle a red in s oftw a re. the two-wire interf a ce interr u pt i s gener a ted b y twif in twcr. the fl a g i s not cle a red b y h a rdw a re when the cpu vector s to the s ervice ro u tine. the s ervice ro u tine norm a lly m us t deter- mine the s t a t us in tw s r a nd re s pond a ccordingly b efore the b it i s cle a red b y s oftw a re. all of the b it s th a t gener a te interr u pt s c a n b e s et or cle a red b y s oftw a re, with the sa me re su lt as tho u gh they h a d b een s et or cle a red b y h a rdw a re. th a t i s , interr u pt s c a n b e gener a ted a nd pending interr u pt s c a n b e c a nceled in s oftw a re.
41 3706c?micro?2/11 at89lp3240/6440 9.1 interrupt response time the interr u pt fl a g s m a y b e s et b y their h a rdw a re in a ny clock cycle. the interr u pt controller poll s the fl a g s in the l as t clock cycle of the in s tr u ction in progre ss . if one of the fl a g s w as s et in the preceding cycle, the po lling cycle will find it a nd the interr u pt s y s tem will gener a te a n lcall to the a ppropri a te s ervice ro u tine as the next in s tr u ction, provided th a t the interr u pt i s not b locked b y a ny of the following condition s : a n interr u pt of eq ua l or higher priority level i s a lre a dy in prog- re ss ; the in s tr u ction in progre ss i s reti or a ny write to the ie, ip, iph, ie2, ip2 or ip2h regi s ter s ; the cpu i s c u rrently forced into idle b y a n iap or fdata write. e a ch of the s e condition s will b lock the gener a tion of the lcall to the interr u pt s ervice ro u tine. the s econd condition en su re s th a t if the in s tr u ction in progre ss i s reti or a ny a cce ss to ie, ip, iph, ie2, ip2 or ip2h, then a t le as t one more in s tr u ction will b e exec u ted b efore a ny interr u pt i s vectored to. the polling cycle i s repe a ted a t the l as t cycle of e a ch in s tr u ction, a nd the v a l u e s polled a re the v a l u e s th a t were pre s ent a t the previo us clock cycle. if a n a ctive interr u pt fl a g i s not b eing s erviced b ec aus e of one of the ab ove condition s a nd i s no longer a ctive when the b locking condition i s removed, the denied interr u pt will not b e s erviced. in other word s , the f a ct th a t the interr u pt fl a g w as once a ctive bu t not s erviced i s not remem b ered. every polling cycle i s new. if a req u e s t i s a ctive a nd condition s a re met for it to b e a cknowledged, a h a rdw a re sub ro u tine c a ll to the req u e s ted s ervice ro u tine will b e the next in s tr u ction exec u ted. the c a ll it s elf t a ke s fo u r cycle s . th us , a minim u m of five complete clock cycle s el a p s ed b etween a ctiv a tion of a n interr u pt req u e s t a nd the b eginning of exec u tion of the fir s t in s tr u ction of the s ervice ro u tine. a longer re s pon s e time re su lt s if the req u e s t i s b locked b y one of the previo us ly li s ted condition s . if a n interr u pt of eq ua l or higher priority level i s a lre a dy in progre ss , the a ddition a l w a it time depend s on the n a t u re of the other interr u pt' s s ervice ro u tine. if the in s tr u ction in progre ss i s not in it s fin a l clock cycle, the a ddition a l w a it time c a nnot b e more th a n 8 cycle s , s ince the longe s t in s tr u ction i s 9 cycle s long. if the in s tr u ction in progre ss i s reti with x s tk, the a ddition a l w a it time c a nnot b e more th a n 14 cycle s ( a m a xim u m of 5 more cycle s to complete the in s tr u ction in progre ss , pl us a m a xim u m of 9 cycle s to complete the next in s tr u ction). th us , in a s ingle-inter- table 9-1. interr u pt vector addre ss e s interrupt source vector address s y s tem re s et r s t or por or bod 0000h extern a l interr u pt 0 ie0 0003h timer 0 overflow tf0 000bh extern a l interr u pt 1 ie1 0013h timer 1 overflow tf1 001bh s eri a l port interr u pt ri or ti 0023h timer 2 interr u pt tf2 or exf2 002bh an a log comp a r a tor interr u pt cfa or cfb 0033h gener a l-p u rpo s e interr u pt gpif 7-0 003bh comp a re/c a pt u re arr a y interr u pt t2ccf 3-0 0043h s eri a l peripher a l interf a ce interr u pt s pif or modf or txe 004bh adc interr u pt adif 0053h two-wire interf a ce interr u pt twif 005bh
42 3706c?micro?2/11 at89lp3240/6440 r u pt s y s tem, the re s pon s e time i s a lw a y s more th a n 5 clock cycle s a nd le ss th a n 21 clock cycle s . s ee fig u re 9-1 a nd fig u re 9-2 . figure 9-1. minim u m interr u pt re s pon s e time figure 9-2. m a xim u m interr u pt re s pon s e time . clock cycle s int0 ie0 15 in s tr u ction lcall 1 s t i s r in s tr. c u r. in s tr. ack. clock cycle s int0 ie0 1 21 in s tr u ction reti mac ab lcall 1 s t i s r in s tr. ack. 615 table 9-2. ie ? interr u pt en ab le regi s ter ie = a 8 h re s et v a l u e = 0000 0000b bit addre ssab le ea ec et2 e s et1 ex1 et0 ex0 bit76543210 symbol function ea glo ba l en ab le/di sab le. all interr u pt s a re di sab led when ea = 0. when ea = 1, e a ch interr u pt s o u rce i s en ab led/di sab led b y s etting /cle a ring it s own en ab le b it. ec comp a r a tor interr u pt en ab le et2 timer 2 interr u pt en ab le e ss eri a l port interr u pt en ab le et1 timer 1 interr u pt en ab le ex1 extern a l interr u pt 1 en ab le et0 timer 0 interr u pt en ab le ex0 extern a l interr u pt 0 en ab le
43 3706c?micro?2/11 at89lp3240/6440 table 9-3. ie2 ? interr u pt en ab le 2 regi s ter ie = b4h re s et v a l u e = xxxx x000b not bit addre ssab le ? ? ? etwi eadc e s pi ecc egp bit76543210 symbol function etwi two-wire interf a ce interr u pt en ab le eadc adc interr u pt en ab le e s pi s eri a l peripher a l interf a ce interr u pt en ab le ecc comp a re/c a pt u re arr a y interr u pt en ab le egp gener a l-p u rpo s e interr u pt en ab le table 9-4. ip ? interr u pt priority regi s ter ip = b 8 h re s et v a l u e = 0000 0000b bit addre ssab le ip0d pc pt2 p s pt1 px1 pt0 px0 bit76543210 symbol function ip0d interr u pt priority 0 di sab le. s et ip0d to 1 to di sab le a ll interr u pt s with priority level zero. cle a r to 0 to en ab le a ll interr u pt s with priority level zero when ea = 1. pc comp a r a tor interr u pt priority low pt2 timer 2 interr u pt priority low p ss eri a l port interr u pt priority low pt1 timer 1 interr u pt priority low px1 extern a l interr u pt 1 priority low pt0 timer 0 interr u pt priority low px0 extern a l interr u pt 0 priority low table 9-5. ip2 ? interr u pt priority 2 regi s ter ip = b5h re s et v a l u e = 0xxx x000b no bit addre ssab le ip2d ? ? ptwi padc p s ppccpgp bit76543210 symbol function ip2d interr u pt priority 2 di sab le. s et ip2d to 1 to di sab le a ll interr u pt s with priority level two. cle a r to 0 to en ab le a ll interr u pt s with priority level two when ea = 1. ptwi two-wire interf a ce interr u pt priority low padc adc interr u pt priority low
44 3706c?micro?2/11 at89lp3240/6440 p s p s eri a l peripher a l interf a ce interr u pt priority low pcc comp a re/c a pt u re arr a y interr u pt priority low pgp gener a l-p u rpo s e interr u pt 0 priority low symbol function table 9-6. iph ? interr u pt priority high regi s ter iph = b7h re s et v a l u e = 0000 0000b not bit addre ssab le ip1d pch pt2h p s h pt1h px1h pt0h px0h bit76543210 symbol function ip1d interr u pt priority 1 di sab le. s et ip1d to 1 to di sab le a ll interr u pt s with priority level one. cle a r to 0 to en ab le a ll interr u pt s with priority level one when ea = 1. pch comp a r a tor interr u pt priority high pt2h timer 2 interr u pt priority high p s h s eri a l port interr u pt priority high pt1h timer 1 interr u pt priority high px1h extern a l interr u pt 1 priority high pt0h timer 0 interr u pt priority high px0h extern a l interr u pt 0 priority high table 9-7. ip2h ? interr u pt priority 2 high regi s ter iph = b6h re s et v a l u e = 0xxx x000b not bit addre ssab le ip3d ? ? ptwh padh p s ph pcch pgph bit76543210 symbol function ip3d interr u pt priority 3 di sab le. s et ip3d to 1 to di sab le a ll interr u pt s with priority level three. cle a r to 0 to en ab le a ll interr u pt s with priority level three when ea = 1. ptwh two-wire interf a ce interr u pt priority high padh adc interr u pt priority high p s ph s eri a l peripher a l interf a ce interr u pt priority high pcch comp a re/c a pt u re arr a y interr u pt priority high pgph gener a l-p u rpo s e interr u pt 0 priority high
45 3706c?micro?2/11 at89lp3240/6440 10. i/o ports the at 8 9lp3240/6440 c a n b e config u red for b etween 35 a nd 3 8 i/o pin s . the ex a ct n u m b er of i/o pin s a v a il ab le depend s on the clock a nd re s et option s as s hown in t ab le 10-1 . 10.1 port configuration all port pin s on the at 8 9lp3240/6440 m a y b e config u red to one of fo u r mode s : q uas i- b idirec- tion a l ( s t a nd a rd 8 051 port o u tp u t s ), p us h-p u ll o u tp u t, open-dr a in o u tp u t, or inp u t-only. port mode s m a y b e ass igned in s oftw a re on a pin- b y-pin bas i s as s hown in t ab le 10-2 us ing the reg- i s ter s li s ted in t ab le 10-3 . the tri s t a te-port u s er f us e determine s the def au lt s t a te of the port pin s . when the f us e i s en ab led, a ll port pin s def au lt to inp u t-only mode a fter re s et. when the f us e i s di sab led, a ll port pin s , with the exception of the a n a log inp u t s , p0.7-0, p2.4, p2.5, p2.6 a nd p2.7, def au lt to q uas i- b idirection a l mode a fter re s et a nd a re we a kly p u lled high. the a n a log inp u t pin s a lw a y s re s et to inp u t-only (tri s t a te) mode. e a ch port pin a l s o h as a s chmitt-triggered inp u t for improved inp u t noi s e rejection. d u ring power-down a ll the s chmitt-triggered inp u t s a re di sab led with the exception of p3.2 (int0 ), p3.3 (int1 ), p4.2 (r s t ), p4.0 (xtal1) a nd p4.1 (xtal2) which m a y b e us ed to w a ke u p the device. therefore, p3.2, p3.3, p4.2, p4.0 a nd p4.1 s ho u ld not b e left flo a ting d u ring power-down. in a ddition a ny pin of port 1 config u red as a gen- er a l-p u rpo s e interr u pt inp u t will a l s o rem a in a ctive d u ring power-down to w a ke- u p the device. the s e interr u pt pin s s ho u ld either b e di sab led b efore entering power-down or they s ho u ld not b e left flo a ting. . . table 10-1. i/o pin config u r a tion s clock source reset option number of i/o pins extern a l cry s t a l or re s on a tor extern a l r s t pin 35 no extern a l re s et 36 extern a l clock extern a l r s t pin 36 no extern a l re s et 37 intern a l rc o s cill a tor extern a l r s t pin 37 no extern a l re s et 3 8 table 10-2. config u r a tion mode s for port x, bit y pxm0.y pxm1.y port mode 00q uas i- b idirection a l 01p us h-p u ll o u tp u t 10inp u t only (high imped a nce) 1 1 open-dr a in o u tp u t table 10-3. port config u r a tion regi s ter s port port data port configuration 0p0 ( 8 0h) p0m0 (bah), p0m1 (bbh) 1 p1 (90h) p1m0 (c2h), p1m1 (c3h) 2 p2 (a0h) p2m0 (c4h), p2m1 (c5h) 3 p3 (b0h) p3m0 (c6h), p3m1 (c7h) 4 p4 (c0h) p4m0 (beh), p4m1 (bfh)
46 3706c?micro?2/11 at89lp3240/6440 10.1.1 quasi-bidirectional output port pin s in q uas i- b idirection a l o u tp u t mode f u nction s imil a r to s t a nd a rd 8 051 port pin s . a q uas i- b idirection a l port c a n b e us ed b oth as a n inp u t a nd o u tp u t witho u t the need to reconfig u re the port. thi s i s po ss i b le b ec aus e when the port o u tp u t s a logic high, it i s we a kly driven, a llowing a n extern a l device to p u ll the pin low. when the pin i s driven low, it i s driven s trongly a nd ab le to s ink a l a rge c u rrent. there a re three p u ll- u p tr a n s i s tor s in the q uas i- b idirection a l o u tp u t th a t s erve different p u rpo s e s . one of the s e p u ll- u p s , c a lled the ?very we a k? p u ll- u p, i s t u rned on whenever the port l a tch for the pin cont a in s a logic ?1?. thi s very we a k p u ll- u p s o u rce s a very s m a ll c u rrent th a t will p u ll the pin high if it i s left flo a ting. a s econd p u ll- u p, c a lled the ?we a k? p u ll- u p, i s t u rned on when the port l a tch for the pin cont a in s a logic ?1? a nd the pin it s elf i s a l s o a t a logic ?1? level. thi s p u ll- u p provide s the prim a ry s o u rce c u rrent for a q uas i- b idirection a l pin th a t i s o u tp u tting a ?1?. if thi s pin i s p u lled low b y a n extern a l device, thi s we a k p u ll- u p t u rn s off, a nd only the very we a k p u ll- u p rem a in s on. in order to p u ll the pin low u nder the s e condition s , the extern a l device h as to s ink eno u gh c u rrent to overpower the we a k p u ll- u p a nd p u ll the port pin b elow it s inp u t thre s hold volt a ge. the third p u ll- u p i s referred to as the ? s trong? p u ll- u p. thi s p u ll- u p i s us ed to s peed u p low-to- high tr a n s ition s on a q uas i- b idirection a l port pin when the port l a tch ch a nge s from a logic ?0? to a logic ?1?. when thi s occ u r s , the s trong p u ll- u p t u rn s on for two cpu clock s q u ickly p u lling the port pin high. the q uas i- b idirection a l port config u r a tion i s s hown in fig u re 10-1 . figure 10-1. q uas i- b idirection a l o u tp u t 10.1.2 input-only mode the inp u t only port config u r a tion i s s hown in fig u re 10-2 . the o u tp u t driver s a re tri s t a ted. the inp u t incl u de s a s chmitt-triggered inp u t for improved inp u t noi s e rejection. the inp u t circ u itry of p3.2, p3.3, p4.2, p4.0 a nd p4.1 i s not di sab led d u ring power-down ( s ee fig u re 10-3 ) a nd there- fore the s e pin s s ho u ld not b e left flo a ting d u ring power-down when config u red in thi s mode. figure 10-2. inp u t only 1 clock del a y (d flip-flop) s trong ver y we a k we a k port pin v cc v cc v cc from port regi s ter inp u t d a t a pwd port pin inp u t d a t a pwd
47 3706c?micro?2/11 at89lp3240/6440 figure 10-3. inp u t circ u it for p3.2, p3.3, p4.0, p4.1 a nd p4.2 10.1.3 open-drain output the open-dr a in o u tp u t config u r a tion t u rn s off a ll p u ll- u p s a nd only drive s the p u ll-down tr a n s i s tor of the port pin when the port l a tch cont a in s a logic ?0?. to b e us ed as a logic o u tp u t, a port con- fig u red in thi s m a nner m us t h a ve a n extern a l p u ll- u p, typic a lly a re s i s tor tied to v dd . the p u ll- down for thi s mode i s the sa me as for the q uas i- b idirection a l mode. the open-dr a in port config u - r a tion i s s hown in fig u re 10-4 . the inp u t circ u itry of p3.2, p3.3, p4.0, p4.1 a nd p4.2 i s not di sab led d u ring power-down ( s ee fig u re 10-3 ) a nd therefore the s e pin s s ho u ld not b e left flo a t- ing d u ring power-down when config u red in thi s mode. figure 10-4. open-dr a in o u tp u t 10.1.4 push-pull output the p us h-p u ll o u tp u t config u r a tion h as the sa me p u ll-down s tr u ct u re as b oth the open-dr a in a nd the q uas i- b idirection a l o u tp u t mode s , bu t provide s a contin u o us s trong p u ll- u p when the port l a tch cont a in s a logic ?1?. the p us h-p u ll mode m a y b e us ed when more s o u rce c u rrent i s needed from a port o u tp u t. the p us h-p u ll port config u r a tion i s s hown in fig u re 10-5 . figure 10-5. p us h-p u ll o u tp u t port pin inp u t d a t a port pin from port regi s ter inp u t d a t a pwd port pin v cc from port regi s ter inp u t d a t a pwd
48 3706c?micro?2/11 at89lp3240/6440 10.2 port analog functions the at 8 9lp3240/6440 incorpor a te s two a n a log comp a r a tor s a nd a n 8 -ch a nnel a n a log-to-digit a l converter. in order to give the b e s t a n a log perform a nce a nd minimize power con su mption, pin s th a t a re b eing us ed for a n a log f u nction s m us t h a ve b oth their digit a l o u tp u t s a nd digit a l inp u t s di sab led. digit a l o u tp u t s a re di sab led b y p u tting the port pin s into the inp u t-only mode as de s cri b ed in ?port config u r a tion? on p a ge 45 . the a n a log inp u t pin s will a lw a y s def au lt to inp u t- only mode a fter re s et reg a rdle ss of the s t a te of the tri s t a te-port f us e. digit a l inp u t s on p2.4, p2.5, p2.6 a nd p2.7 a re di sab led whenever a n a n a log comp a r a tor i s en ab led b y s etting the cena or cenb b it s in ac s ra a nd ac s rb a nd th a t pin i s config u red for inp u t-only mode. to us e a n a n a log inp u t pin as a high-imped a nce digit a l inp u t while a comp a r a - tor i s en ab led, th a t pin s ho u ld b e config u red in open-dr a in mode a nd the corre s ponding port regi s ter b it s ho u ld b e s et to 1. digit a l inp u t s on port 0 a re di sab led for e a ch pin config u red for inp u t-only mode whenever the adc i s en ab led b y s etting the adce b it a nd cle a ring the dac b it in dadc. to us e a ny port 0 inp u t pin as a high-imped a nce digit a l inp u t while the adc i s en ab led, th a t pin s ho u ld b e config- u red in open-dr a in mode a nd the corre s ponding port regi s ter b it s ho u ld b e s et to 1. when dac mode i s en ab led, p2.2 a nd p2.3 a re forced to inp u t-only mode. 10.3 port read-modify-write a re a d from a port will re a d either the s t a te of the pin s or the s t a te of the port regi s ter depending on which in s tr u ction i s us ed. s imple re a d in s tr u ction s will a lw a y s a cce ss the port pin s directly. re a d-modify-write in s tr u ction s , which re a d a v a l u e, po ss i b ly modify it, a nd then write it ba ck, will a lw a y s a cce ss the port regi s ter. thi s incl u de s b it write in s tr u ction s su ch as clr or s etb as they a ct ua lly re a d the entire port, modify a s ingle b it, then write the d a t a ba ck to the entire port. s ee t ab le 10-4 for a complete li s t of re a d-modify-write in s tr u ction which m a y a cce ss the port s . table 10-4. port re a d-modify-write in s tr u ction s mnemonic instruction example anl logic a l and anl p1, a orl logic a l or orl p1, a xrl logic a l ex-or xrl p1, a jbc j u mp if b it s et a nd cle a r b it jbc p3.0, label cpl complement b it cpl p3.1 inc increment inc p1 dec decrement dec p3 djnz decrement a nd j u mp if not zero djnz p3, label mov px.y, c move c a rry to b it y of port x mov p1.0, c clr px.y cle a r b it y of port x clr p1.1 s etb px.y s et b it y of port x s etb p3.2
49 3706c?micro?2/11 at89lp3240/6440 10.4 port alternate functions mo s t gener a l-p u rpo s e digit a l i/o pin s of the at 8 9lp3240/6440 s h a re f u nction a lity with the v a ri- o us i/o s needed for the peripher a l u nit s . t ab le 10-6 li s t s the a ltern a te f u nction s of the port pin s . altern a te f u nction s a re connected to the pin s in a logic and f as hion. in order to en ab le the a ltern a te f u nction on a port pin, th a t pin m us t h a ve a ?1? in it s corre s ponding port regi s ter b it, otherwi s ethe inp u t/o u tp u t will a lw a y s b e ?0?. however, a ltern a te f u nction s m a y b e tempor a rily forced to ?0? b y cle a ring the ass oci a ted port b it, provided th a t the pin i s not in inp u t-only mode. f u rthermore, e a ch pin m us t b e config u red for the correct inp u t/o u tp u t mode as req u ired b y it s peripher a l b efore it m a y b e us ed as su ch. t ab le 10-5 s how s how to config u re a generic pin for us e with a n a ltern a te f u nction. table 10-5. altern a te f u nction config u r a tion s for pin y of port x pxm0.y pxm1.y px.y i/o mode 00 1 b idirection a l (intern a l p u ll- u p) 01 1o u tp u t 10 xinp u t 11 1 b idirection a l (extern a l p u ll- u p) table 10-6. port pin altern a te f u nction s port pin configuration bits alternate function notes pxm0.y pxm1.y p0.0 p0m0.0 p0m1.0 ad0 a u tom a tic config u r a tion adc0 inp u t-only p0.1 p0m0.1 p0m1.1 ad1 a u tom a tic config u r a tion adc1 inp u t-only p0.2 p0m0.2 p0m1.2 ad2 a u tom a tic config u r a tion adc2 inp u t-only p0.3 p0m0.3 p0m1.3 ad3 a u tom a tic config u r a tion adc3 inp u t-only p0.4 p0m0.4 p0m1.4 ad4 a u tom a tic config u r a tion adc4 inp u t-only p0.5 p0m0.5 p0m1.5 ad5 a u tom a tic config u r a tion adc5 inp u t-only p0.6 p0m0.6 p0m1.6 ad6 a u tom a tic config u r a tion adc6 inp u t-only p0.7 p0m0.7 p0m1.7 ad7 a u tom a tic config u r a tion adc7 inp u t-only p1.0 p1m0.0 p1m1.0 t2 gpi0 p1.1 p1m0.1 p1m1.1 t2ex gpi1
50 3706c?micro?2/11 at89lp3240/6440 p1.2 p1m0.2 p1m1.2 s da open-dr a in gpi2 p1.3 p1m0.3 p1m1.3 s cl open-dr a in gpi3 p1.4 p1m0.4 p1m1.4 ss gpi4 p1.5 p1m0.5 p1m1.5 mo s i gpi5 p1.6 p1m0.6 p1m1.6 mi s o gpi6 p1.7 p1m0.7 p1m1.7 s ck gpi7 p2.0 p2m0.0 p2m1.0 cca p2.1 p2m0.1 p2m1.1 ccb p2.2 p2m0.2 p2m1.2 ccc da+ inp u t-only p2.3 p2m0.3 p2m1.3 ccd da- inp u t-only p2.4 p2m0.4 p2m1.4 ain0 inp u t-only p2.5 p2m0.5 p2m1.5 ain1 inp u t-only p2.6 p2m0.6 p2m1.6 ain2 inp u t-only p2.7 p2m0.7 p2m1.7 ain3 inp u t-only p3.0 p3m0.0 p3m1.0 rxd p3.1 p3m0.1 p3m1.1 txd p3.2 p3m0.2 p3m1.2 int0 p3.3 p3m0.3 p3m1.3 int1 p3.4 p3m0.4 p3m1.4 t0 p3.5 p3m0.5 p3m1.5 t1 p3.6 p3m0.6 p3m1.6 wr p3.7 p3m0.7 p3m1.7 rd p4.2 p3m0.5 p3m1.5 r s t r s t m us t b e di sab led to us e p4.2 p4.6 not config u r ab le cmpa pin i s tied to comp a r a tor o u tp u t p4.7 not config u r ab le cmpb pin i s tied to comp a r a tor o u tp u t table 10-6. port pin altern a te f u nction s port pin configuration bits alternate function notes pxm0.y pxm1.y
51 3706c?micro?2/11 at89lp3240/6440 11. enhanced timer 0 and timer 1 with pwm the at 8 9lp3240/6440 h as two 16- b it timer/co u nter s , timer 0 a nd timer 1, with the following fe a t u re s : ? two 16- b it timer/co u nter s with 16- b it relo a d regi s ter s ? two independent 8 - b it preci s ion pwm o u tp u t s with 8 - b it pre s c a ler s ?uart or s pi bau d r a te gener a tion us ing timer 1 ?o u tp u t pin toggle on timer overflow ? s plit timer mode a llow s for three s ep a r a te timer s (2 8 - b it, 1 16- b it) ?g a ted mode s a llow timer s to r u n/h a lt bas ed on a n extern a l inp u t timer 0 a nd timer 1 h a ve s imil a r mode s of oper a tion. a s timer s , the timer regi s ter s incre as e every clock cycle b y def au lt. th us , the regi s ter s co u nt clock cycle s . s ince a clock cycle con s i s t s of one o s cill a tor period, the co u nt r a te i s eq ua l to the o s cill a tor freq u ency. the timer r a te c a n b e pre s c a led b y a v a l u e b etween 1 a nd 16 us ing the timer pre s c a ler ( s ee t ab le 6-2 on p a ge 33 ). both timer s s h a re the sa me pre s c a ler. a s co u nter s , the timer regi s ter s a re incremented in re s pon s e to a 1-to-0 tr a n s ition a t the corre- s ponding inp u t pin s , t0 or t1. the extern a l inp u t i s sa mpled every clock cycle. when the sa mple s s how a high in one cycle a nd a low in the next cycle, the co u nt i s incremented. the new co u nt v a l u e a ppe a r s in the regi s ter d u ring the cycle following the one in which the tr a n s ition w as detected. s ince 2 clock cycle s a re req u ired to recognize a 1-to-0 tr a n s ition, the m a xim u m co u nt r a te i s 1/2 of the o s cill a tor freq u ency. there a re no re s triction s on the d u ty cycle of the inp u t s ig- n a l, bu t it s ho u ld b e held for a t le as t one f u ll clock cycle to en su re th a t a given level i s sa mpled a t le as t once b efore it ch a nge s . f u rthermore, the timer or co u nter f u nction s for timer 0 a nd timer 1 h a ve fo u r oper a ting mode s : v a ri ab le width timer, 16- b it au to-relo a d timer, 8 - b it au to-relo a d timer, a nd s plit timer. the control b it s c/t in the s peci a l f u nction regi s ter tmod s elect the timer or co u nter f u nction. the b it p a ir s (m1, m0) in tmod s elect the oper a ting mode s . table 11-1. timer 0/1 regi s ter su mm a ry name address purpose bit-addressable tcon 88 h control y tmod 8 9h mode n tl0 8 ah timer 0 low- b yte n tl1 8 bh timer 1 low- b yte n th0 8 ch timer 0 high- b yte n th1 8 dh timer 1 high- b yte n tconb 91h mode n rl0 92h timer 0 relo a d low- b yte n rl1 93h timer 1 relo a d low- b yte n rh0 94h timer 0 relo a d high- b yte n rh1 95h timer 1 relo a d high- b yte n
52 3706c?micro?2/11 at89lp3240/6440 11.1 mode 0 ? variable width timer/counter both timer s in mode 0 a re 8 - b it co u nter s with a v a ri ab le pre s c a ler. the pre s c a ler m a y v a ry from 1 to 8 b it s depending on the p s c b it s in tconb, giving the timer a r a nge of 9 to 16 b it s . by def au lt the timer i s config u red as a 13- b it timer comp a ti b le to mode 0 in the s t a nd a rd 8 051. fig u re 11-1 s how s the mode 0 oper a tion as it a pplie s to timer 1 in 13- b it mode. a s the co u nt roll s over from a ll ?1? s to a ll ?0? s , it s et s the timer interr u pt fl a g tf1. the co u nter inp u t i s en ab led to the timer when tr1 = 1 a nd either gate1 = 0 or int1 =1. s etting gate1 = 1 a llow s the timer to b e controlled b y extern a l inp u t int1 , to f a cilit a te p u l s e width me asu rement s . tr1 i s a control b it in the s peci a l f u nction regi s ter tcon. gate1 i s in tmod. the 13- b it regi s ter con- s i s t s of a ll 8 b it s of th1 a nd the lower 5 b it s of tl1. the u pper 3 b it s of tl1 a re indetermin a te a nd s ho u ld b e ignored. s etting the r u n fl a g (tr1) doe s not cle a r the regi s ter s . note: rh1/rl1 a re not req u ired b y timer 1 d u ring mode 0 a nd m a y b e us ed as tempor a ry s tor a ge regi s ter s . figure 11-1. timer/co u nter 1 mode 0: v a ri ab le width co u nter mode 0 oper a tion i s the sa me for timer 0 as for timer 1, except th a t tr0, tf0, gate0 a nd int0 repl a ce the corre s ponding timer 1 s ign a l s in fig u re 11-1 . there a re two different c/t b it s , one for timer 1 (tmod.6) a nd one for timer 0 (tmod.2). 11.2 mode 1 ? 16-bit auto -reload timer/counter in mode 1 the timer s a re config u red for 16- b it au to-relo a d. the timer regi s ter i s r u n with a ll 16 b it s . the 16- b it relo a d v a l u e i s s tored in the high a nd low relo a d regi s ter s (rh1/rl1). the clock i s a pplied to the com b ined high a nd low timer regi s ter s (th1/tl1). a s clock p u l s e s a re received, the timer co u nt s u p: 0000h, 0001h, 0002h, etc. an overflow occ u r s on the ffffh-to- 0000h tr a n s ition, u pon which the timer regi s ter i s relo a ded with the v a l u e from rh1/rl1 a nd the overflow fl a g b it in tcon i s s et. s ee fig u re 11-2 . the relo a d regi s ter s def au lt to 0000h, which give s the f u ll 16- b it timer period comp a ti b le with the s t a nd a rd 8 051. mode 1 oper a tion i s the sa me for timer/co u nter 0. mode 0: time-o u t period 256 2 p s c0 1 + o s cill a tor freq u ency ------------------------------------------------------ - tp s 1 + () = o s c t1 pin tr1 gate1 int1 pin tl1 ( 8 bit s ) control interr u pt c/t = 0 c/t = 1 p s c1 th1 ( 8 bit s ) tf1 tp s mode 1: time-o u t period 65536 rh0 rl0 {,} ? () o s cill a tor freq u ency --------------------------------------------------------- tp s 1 + () =
53 3706c?micro?2/11 at89lp3240/6440 figure 11-2. timer/co u nter 1 mode 1: 16- b it a u to-relo a d 11.3 mode 2 ? 8-bit auto -reload timer/counter mode 2 config u re s the timer regi s ter as a n 8 - b it co u nter (tl1) with au tom a tic relo a d, as s hown in fig u re 11-3 . overflow from tl1 not only s et s tf1, bu t a l s o relo a d s tl1 with the content s of th1, which i s pre s et b y s oftw a re. the relo a d le a ve s th1 u nch a nged. mode 2 oper a tion i s the sa me for timer/co u nter 0. figure 11-3. timer/co u nter 1 mode 2: 8 - b it a u to-relo a d note: rh1/rl1 a re not req u ired b y timer 1 d u ring mode 2 a nd m a y b e us ed as tempor a ry s tor a ge regi s ter s . 11.4 mode 3 ? 8-bit split timer timer 1 in mode 3 s imply hold s it s co u nt. the effect i s the sa me as s etting tr1 = 0. timer 0 in mode 3 e s t ab li s he s tl0 a nd th0 as two s ep a r a te co u nter s . the logic for mode 3 on timer 0 i s s hown in fig u re 11-4 . tl0 us e s the timer 0 control b it s : c/t, gate0, tr0, int0 , a nd tf0. th0 i s locked into a timer f u nction (co u nting clock cycle s ) a nd t a ke s over the us e of tr1 a nd tf1 from timer 1. th us , th0 now control s the timer 1 interr u pt. while timer 0 i s in mode 3, timer 1 will s till o b ey it s s etting s in tmod bu t c a nnot gener a te a n interr u pt. o s c t1 pin tr1 gate1 int1 pin tl1 ( 8 bit s ) control interr u pt c/t = 0 c/t =1 th1 ( 8 bit s ) tf1 rl1 ( 8 bit s ) rh1 ( 8 bit s ) relo a d tp s mode 2: time-o u t period 256 th0 ? () o s cill a tor freq u ency ------------------------------------------------------ - tp s 1 + () = o s c t1 pin tr1 gate1 tf1 tl1 ( 8 bit s ) th1 ( 8 bit s ) control relo a d interr u pt int0 pin c/t = 0 c/t = 1 tp s
54 3706c?micro?2/11 at89lp3240/6440 mode 3 i s for a pplic a tion s req u iring a n extr a 8 - b it timer or co u nter. with timer 0 in mode 3, the at 8 9lp3240/6440 c a n a ppe a r to h a ve fo u r timer/co u nter s . when timer 0 i s in mode 3, timer 1 c a n b e t u rned on a nd off b y s witching it o u t of a nd into it s own mode 3. in thi s c as e, timer 1 c a n s till b e us ed b y the s eri a l port as a bau d r a te gener a tor or in a ny a pplic a tion not req u iring a n interr u pt. figure 11-4. timer/co u nter 0 mode 3: two 8 - b it co u nter s note: rh0/rl0 a re not req u ired b y timer 0 d u ring mode 3 a nd m a y b e us ed as tempor a ry s tor a ge regi s ter s . . control interrupt control interrupt (8 bits) (8 bits) c/t = 0 c/t =1 t0 pin gate0 int0 pin tps tps table 11-2. tcon ? timer/co u nter control regi s ter tcon = 88 h re s et v a l u e = 0000 0000b bit addre ssab le tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 bit76543210 symbol function tf1 timer 1 overflow fl a g. s et b y h a rdw a re on timer/co u nter overflow. cle a red b y h a rdw a re when the proce ss or vector s to interr u pt ro u tine. tr1 timer 1 r u n control b it. s et/cle a red b y s oftw a re to t u rn timer/co u nter on/off. tf0 timer 0 overflow fl a g. s et b y h a rdw a re on timer/co u nter overflow. cle a red b y h a rdw a re when the proce ss or vector s to interr u pt ro u tine. tr0 timer 0 r u n control b it. s et/cle a red b y s oftw a re to t u rn timer/co u nter on/off. ie1 interr u pt 1 edge fl a g. s et b y h a rdw a re when extern a l interr u pt edge detected. cle a red when interr u pt proce ss ed. it1 interr u pt 1 type control b it. s et/cle a red b y s oftw a re to s pecify f a lling edge/low level triggered extern a l interr u pt s . ie0 interr u pt 0 edge fl a g. s et b y h a rdw a re when extern a l interr u pt edge detected. cle a red when interr u pt proce ss ed. it0 interr u pt 0 type control b it. s et/cle a red b y s oftw a re to s pecify f a lling edge/low level triggered extern a l interr u pt s .
55 3706c?micro?2/11 at89lp3240/6440 table 11-3. tmod ? timer/co u nter mode control regi s ter tmod addre ss = 0 8 9h re s et v a l u e = 0000 0000b not bit addre ssab le gate1 c/t1 t1m1 t1m0 gate0 c/t0 t0m0 t0m1 bit76543210 symbol function gate1 timer 1 g a ting control. when s et, timer/co u nter 1 i s en ab led only while int1 pin i s high a nd tr1 control pin i s s et. when cle a red, timer 1 i s en ab led whenever tr1 control b it i ss et. c/t1 timer or co u nter s elector 1. cle a red for timer oper a tion (inp u t from intern a l s y s tem clock). s et for co u nter oper a tion (inp u t from t1 inp u t pin). c/t1 m us t b e zero when us ing timer 1 in pwm mode. t1m1 t1m0 timer 1 oper a ting mode mode t1m1 t1m0 operation 000v a ri ab le 9?16- b it timer mode. 8 - b it timer/co u nter th1 with tl1 as 1? 8 - b it pre s c a ler. 101 16- b it a u to-relo a d mode. th1 a nd tl1 a re c as c a ded to form a 16- b it timer/co u nter th a t i s relo a ded with rh1 a nd rl1 e a ch time it overflow s . 210 8 - b it a u to relo a d mode. th1 hold s a v a l u e which i s relo a ded into 8 - b it timer/co u nter tl1 e a ch time it overflow s . 311timer/co u nter 1 i s s topped gate0 timer 0 g a ting control. when s et, timer/co u nter 0 i s en ab led only while int0 pin i s high a nd tr0 control pin i s s et. when cle a red, timer 0 i s en ab led whenever tr0 control b it i ss et. c/t0 timer or co u nter s elector 0. cle a red for timer oper a tion (inp u t from intern a l s y s tem clock). s et for co u nter oper a tion (inp u t from t0 inp u t pin). c/t0 m us t b e zero when us ing timer 0 in pwm mode. t0m1 t0m0 timer 0 oper a ting mode mode t0m1 t0m0 operation 000v a ri ab le 9?16- b it timer mode. 8 - b it timer/co u nter th0 with tl0 as 1? 8 - b it pre s c a ler. 101 16- b it a u to-relo a d mode. th0 a nd tl0 a re c as c a ded to form a 16- b it timer/co u nter th a t i s relo a ded with rh0 a nd rl0 e a ch time it overflow s . 210 8 - b it a u to relo a d mode. th0 hold s a v a l u e which i s relo a ded into 8 - b it timer/co u nter tl0 e a ch time it overflow s . 311 s plit timer mode. tl0 i s a n 8 - b it timer/co u nter controlled b y the s t a nd a rd timer 0 control b it s . th0 i s a n 8 - b it timer only controlled b y timer 1 control b it s .
56 3706c?micro?2/11 at89lp3240/6440 11.5 pulse width modulation on the at 8 9lp3240/6440, timer 0 a nd timer 1 m a y b e independently config u red as 8 - b it as ymmetric a l (edge- a ligned) p u l s e width mod u l a tor s (pwm) b y s etting the pwm0en or pwm1en b it s in tconb, re s pectively. in pwm mode the gener a ted w a veform i s o u tp u t on the timer' s inp u t pin, t0 or t1. therefore, c/tx m us t b e s et to ?0? when in pwm mode a nd the t0 (p3.4) a nd t1 (p3.5) m us t b e config u red in a n o u tp u t mode. the timer overflow fl a g s a nd interr u pt s will contin u e to f u nction while in pwm mode a nd timer 1 m a y s till gener a te the bau d r a te for the uart. the timer gate f u nction a l s o work s in pwm mode, a llowing the o u tp u t to b e h a lted b y a n extern a l inp u t. e a ch pwm ch a nnel h as fo u r mode s s elected b y the mode b it s in tmod. an ex a mple w a veform for timer 0 in pwm mode 0 i s s hown in fig u re 11-5 . th0 a ct s as a n 8 - b it co u nter while rh0 s tore s the 8 - b it comp a re v a l u e. when th0 i s 00h the pwm o u tp u t i s s et high. when the th0 co u nt re a che s the v a l u e s tored in rh0 the pwm o u tp u t i s s et low. therefore, the p u l s e width i s proportion a l to the v a l u e in rh0. to prevent glitche s , write s to rh0 only t a ke effect on the ffh to 00h overflow of th0. s etting rh0 to 00h will keep the pwm o u tp u t low. figure 11-5. 8 - b it a s ymmetric a l p u l s e width mod u l a tion table 11-4. tconb ? timer/co u nter control regi s ter b tconb = 91h re s et v a l u e = 0010 0100b not bit addre ssab le pwm1en pwm0en p s c12 p s c11 p s c10 p s c02 p s c01 p s c00 bit76543210 symbol function pwm1en config u re s timer 1 for p u l s e width mod u l a tion o u tp u t on t1 (p3.5). pwm0en config u re s timer 0 for p u l s e width mod u l a tion o u tp u t on t0 (p3.4). p s c12 p s c11 p s c10 pre s c a ler for timer 1 mode 0. the n u m b er of a ctive b it s in tl1 eq ua l s p s c1 + 1. after re s et p s c1 = 100b which en ab le s 5 b it s of tl1 for comp a ti b ility with the 13- b it mode 0 in at 8 9 s 2051. p s c02 p s c01 p s c00 pre s c a ler for timer 0 mode 0. the n u m b er of a ctive b it s in tl0 eq ua l s p s c0 + 1. after re s et p s c0 = 100b which en ab le s 5 b it s of tl0 for comp a ti b ility with the 13- b it mode 0 in at 8 9c52. ffh 00h rh0 (p3.4)t0 tf0 s et th0 time
57 3706c?micro?2/11 at89lp3240/6440 11.5.1 mode 0 ? 8-bit pwm with 8-bit logarithmic prescaler in mode 0, tlx a ct s as a log a rithmic pre s c a ler driving 8 - b it co u nter thx ( s ee fig u re 11-6 ). the p s cx b it s in tconb control the pre s c a ler v a l u e. on thx overflow, the d u ty cycle v a l u e in rhx i s tr a n s ferred to ocrx a nd the o u tp u t pin i s s et high. when the co u nt in thx m a tche s ocrx, the o u tp u t pin i s cle a red low. the following form u l as give the o u tp u t freq u ency a nd d u ty cycle for timer 0 in pwm mode 0. timer 1 in pwm mode 0 i s identic a l to timer 0. figure 11-6. timer/co u nter 1 pwm mode 0 11.5.2 mode 1 ? 8-bit pwm with 8-bit linear prescaler in mode 1, tlx provide s line a r pre s c a ling with a n 8 - b it au to-relo a d from rlx ( s ee fig u re 11-7 on p a ge 5 8 ). on tlx overflow, tlx i s lo a ded with the v a l u e of rlx. thx a ct s as a n 8 - b it co u nter. on thx overflow, the d u ty cycle v a l u e in rhx i s tr a n s ferred to ocrx a nd the o u tp u t pin i s s et high. when the co u nt in thx m a tche s ocrx, the o u tp u t pin i s cle a red low. the following form u l as give the o u tp u t freq u ency a nd d u ty cycle for timer 0 in pwm mode 1. timer 1 in pwm mode 1 i s identic a l to timer 0. 11.5.3 mode 2 ? 8-bit frequency generator timer 0 in pwm mode 2 f u nction s as a n 8 - b it a u to-relo a d timer, the sa me as norm a l mode 2, with the exception th a t the o u tp u t pin t0 i s toggled a t every tl0 overflow ( s ee fig u re 11- 8 a nd fig u re 11-9 on p a ge 5 8 ). timer 1 in pwm mode 2 i s identic a l to timer 0. pwm mode 2 c a n b e us ed to o u tp u t a s q ua re w a ve of v a rying freq u ency. thx a ct s as a n 8 - b it co u nter. the following form u l a give s the o u tp u t freq u ency for timer 0 in pwm mode 2. mode 0: f out o s cill a tor freq u ency 256 2 p s c0 1 + ------------------------------------------------------ - 1 tp s 1 + -------------------- - = d u ty cycle % 100 rh0 256 ----------- - = o s c tr1 gate1 int1 pin tl1 ( 8 bit s ) control p s c1 th1 ( 8 bit s ) ocr1 rh1 ( 8 bit s ) = t1 tp s mode 1: f out o s cill a tor freq u ency 256 256 rl0 ? () ------------------------------------------------------ - 1 tp s 1 + -------------------- - = d u ty cycle % 100 rh0 256 ----------- - = mode 2: f out o s cill a tor freq u ency 2256th0 ? () ------------------------------------------------------ - 1 tp s 1 + -------------------- - =
58 3706c?micro?2/11 at89lp3240/6440 figure 11-7. timer/co u nter 1 pwm mode 1 figure 11-8. timer/co u nter 1 pwm mode 2 note: {rh0 & rl0}/{rh1 & rl1} a re not req u ired b y timer 0/timer 1 d u ring pwm mode 2 a nd m a y b e us ed as tempor a ry s tor a ge regi s ter s . figure 11-9. pwm mode 2 w a veform o s c tr1 gate1 int1 pin tl1 ( 8 bit s ) control th1 ( 8 bit s ) ocr1 rh1 ( 8 bit s ) = t1 rl1 ( 8 bit s ) tp s o s c tr1 gate1 int1 pin tl1 ( 8 bit s ) control t1 th1 ( 8 bit s ) tp s tx thx ffh
59 3706c?micro?2/11 at89lp3240/6440 11.5.4 mode 3 ? split 8-bit pwm timer 1 in pwm mode 3 s imply hold s it s co u nt. the effect i s the sa me as s etting tr1 = 0. timer 0 in pwm mode 3 e s t ab li s he s tl0 a nd th0 as two s ep a r a te pwm co u nter s in a m a nner s imil a r to norm a l mode 3. pwm mode 3 on timer 0 i s s hown in fig u re 11-10 . only the timer pre s c a ler i s a v a il ab le to ch a nge the o u tp u t freq u ency d u ring pwm mode 3. tl0 c a n us e the timer 0 control b it s : gate, tr0, int0 , pwm0en a nd tf0. th0 i s locked into a timer f u nction a nd us e s tr1, pwm1en a nd tf1. rl0 provide s the d u ty cycle for tl0 a nd rh0 provide s the d u ty cycle for th0. pwm mode 3 i s for a pplic a tion s req u iring a s ingle pwm ch a nnel a nd two timer s , or two pwm ch a nnel s a nd a n extr a timer or co u nter. with timer 0 in pwm mode 3, the at 8 9lp3240/6440 c a n a ppe a r to h a ve fo u r timer/co u nter s . when timer 0 i s in pwm mode 3, timer 1 c a n b e t u rned on a nd off b y s witching it o u t of a nd into it s own mode 3. in thi s c as e, timer 1 c a n s till b e us ed b y the s eri a l port as a bau d r a te gener a tor or in a ny a pplic a tion not req u iring a n interr u pt. the following form u l as give the o u tp u t freq u ency a nd d u ty cycle for timer 0 in pwm mode 3. figure 11-10. timer/co u nter 0 pwm mode 3 mode 3: f out o s cill a tor freq u ency 256 ------------------------------------------------------ - 1 tp s 1 + -------------------- - = mode 3, t0: d u ty cycle % 100 rl0 256 ---------- - = mode 3, t1: d u ty cycle % 100 rh0 256 ----------- - = o s c tr0 gate0 int0 pin control tl0 ( 8 bit s ) ocr0 rl0 ( 8 bit s ) = t0 o s c th0 ( 8 bit s ) ocr1 rh0 ( 8 bit s ) = t1 tr1 tp s tp s
60 3706c?micro?2/11 at89lp3240/6440 12. enhanced timer 2 the at 8 9lp3240/6440 incl u de s a 16- b it timer/co u nter 2 with the following fe a t u re s : ?16- b it timer/co u nter with one 16- b it relo a d/c a pt u re regi s ter ? one extern a l relo a d/c a pt u re inp u t ? up/down co u nting mode with extern a l direction control ?uart bau d r a te gener a tion ?o u tp u t-pin toggle on timer overflow ?d ua l s lope s ymmetric oper a ting mode s timer 2 i s a 16- b it timer/co u nter th a t c a n oper a te as either a timer or a n event co u nter. the type of oper a tion i s s elected b y b it c/t2 in the s fr t2con. timer 2 h as three oper a ting mode s : c a pt u re, au to-relo a d ( u p or down co u nting), a nd bau d r a te gener a tor. the mode s a re s elected b y b it s in t2con a nd t2mod, as s hown in t ab le 12-3 . timer 2 a l s o s erve s as the time bas e for the comp a re/c a pt u re arr a y ( s ee s ection 13. ?comp a re/c a pt u re arr a y? on p a ge 69 ). timer 2 con s i s t s of two 8 - b it regi s ter s , th2 a nd tl2. in the timer f u nction, the regi s ter i s incre- mented every clock cycle. s ince a clock cycle con s i s t s of one o s cill a tor period, the co u nt r a te i s eq ua l to the o s cill a tor freq u ency. the timer r a te c a n b e pre s c a led b y a v a l u e b etween 1 a nd 16 us ing the timer pre s c a ler ( s ee t ab le 6-2 on p a ge 33 ). in the co u nter f u nction, the regi s ter i s incremented in re s pon s e to a 1-to-0 tr a n s ition a t it s corre- s ponding extern a l inp u t pin, t2. in thi s f u nction, the extern a l inp u t i s sa mpled every clock cycle. when the sa mple s s how a high in one cycle a nd a low in the next cycle, the co u nt i s incre- mented. the new co u nt v a l u e a ppe a r s in the regi s ter d u ring the cycle following the one in which the tr a n s ition w as detected. s ince two clock cycle s a re req u ired to recognize a 1-to-0 tr a n s ition, the m a xim u m co u nt r a te i s 1/2 of the o s cill a tor freq u ency. to en su re th a t a given level i s sa m- pled a t le as t once b efore it ch a nge s , the level s ho u ld b e held for a t le as t one f u ll clock cycle. the following definition s for timer 2 a re us ed in the subs eq u ent p a r a gr a ph s : table 12-1. timer 2 oper a ting mode s rclk + tclk cp/rl2 dcen t2oe tr2 mode 0000116- b it a u to-relo a d 0010116- b it a u to-relo a d up-down 01x0116- b it c a pt u re 1 xxx1b au d r a te gener a tor xxx11freq u ency gener a tor x x x x 0 (off) table 12-2. timer 2 definition s symbol definition min 0000h max ffffh bottom 16- b it v a l u e of {rcap2h,rcap2l} ( s t a nd a rd mode s ) top 16- b it v a l u e of {rcap2h,rcap2l} (enh a nced mode s )
61 3706c?micro?2/11 at89lp3240/6440 12.1 timer 2 registers control a nd s t a t us b it s for timer 2 a re cont a ined in regi s ter s t2con ( s ee t ab le 12-3 ) a nd t2mod ( s ee t ab le 12-4 ). the regi s ter p a ir {th2, tl2} a t a ddre ss e s 0cdh a nd 0cch a re the 16- b it timer regi s ter for timer 2. the regi s ter p a ir {rcap2h, rcap2l} a t a ddre ss e s 0cbh a nd 0cah a re the 16- b it c a pt u re/relo a d regi s ter for timer 2 in c a pt u re a nd au to-relo a d mode s . table 12-3. t2con ? timer/co u nter 2 control regi s ter t2con addre ss = 0c 8 h re s et v a l u e = 0000 0000b bit addre ssab le tf2 exf2 rclk tclk exen2 tr2 c/t2 cp/rl2 bit76543210 symbol function tf2 timer 2 overflow fl a g s et b y a timer 2 overflow a nd m us t b e cle a red b y s oftw a re. tf2 will not b e s et when either rclk = 1 or tclk = 1. exf2 timer 2 extern a l fl a g s et when either a c a pt u re or relo a d i s c aus ed b y a neg a tive tr a n s ition on t2ex a nd exen2 = 1. when timer 2 interr u pt i s en ab led, exf2 = 1 will c aus e the cpu to vector to the timer 2 interr u pt ro u tine. exf2 m us t b e cle a red b y s oftw a re. exf2 doe s not c aus e a n interr u pt in u p/down co u nter mode (dcen = 1) or d ua l- s lope mode. rclk receive clock en ab le. when s et, c aus e s the s eri a l port to us e timer 2 overflow p u l s e s for it s receive clock in s eri a l port mode s 1 a nd 3. rclk = 0 c aus e s timer 1 overflow s to b e us ed for the receive clock. tclk tr a n s mit clock en ab le. when s et, c aus e s the s eri a l port to us e timer 2 overflow p u l s e s for it s tr a n s mit clock in s eri a l port mode s 1 a nd 3. tclk = 0 c aus e s timer 1 overflow s to b e us ed for the tr a n s mit clock. exen2 timer 2 extern a l en ab le. when s et, a llow s a c a pt u re or relo a d to occ u r as a re su lt of a neg a tive tr a n s ition on t2ex if timer 2 i s not b eing us ed to clock the s eri a l port. exen2 = 0 c aus e s timer 2 to ignore event s a t t2ex. tr2 s t a rt/ s top control for timer 2. tr2 = 1 s t a rt s the timer. c/t2 timer or co u nter s elect for timer 2. c/t2 = 0 for timer f u nction. c/t2 = 1 for extern a l event co u nter (f a lling edge triggered). cp/rl2 c a pt u re/relo a d s elect. cp/rl2 = 1 c aus e s c a pt u re s to occ u r on neg a tive tr a n s ition s a t t2ex if exen2 = 1. cp/rl2 = 0 c aus e s au tom a tic relo a d s to occ u r when timer 2 overflow s or neg a tive tr a n s ition s occ u r a t t2ex when exen2 = 1. when either rclk or tclk = 1, thi s b it i s ignored a nd the timer i s forced to au to-relo a d on timer 2 overflow. table 12-4. t2mod ? timer 2 mode control regi s ter t2mod addre ss = 0c9h re s et v a l u e = 0000 0000b not bit addre ssab le ph s dph s 2ph s 1ph s 0 t2cm1 t2cm0 t2oe dcen bit76543210 symbol function ph s d cca ph as e direction. for ph as e mode s with 3 or 4 ch a nnel s , ph s d determine s the direction th a t the ch a nnel s a re cycled thro u gh. ph s d a l s o determine s the initi a l ph as e rel a tion s hip for 2 ph as e mode s . phsd direction 0 or or 1 or or abab
62 3706c?micro?2/11 at89lp3240/6440 12.2 capture mode in the c a pt u re mode, timer 2 i s a fixed 16- b it timer or co u nter th a t co u nt s u p from min to max. an overflow from max to min s et s b it tf2 in t2con. if exen2 = 1, a 1-to-0 tr a n s ition a t exter- n a l inp u t t2ex a l s o c aus e s the c u rrent v a l u e in th2 a nd tl2 to b e c a pt u red into rcap2h a nd rcap2l, re s pectively. in a ddition, the tr a n s ition a t t2ex c aus e s b it exf2 in t2con to b e s et. the exf2 a nd tf2 b it s c a n gener a te a n interr u pt. c a pt u re mode i s ill us tr a ted in fig u re 12-1 . the timer 2 overflow r a te in c a pt u re mode i s given b y the following eq ua tion: ph s [2-0] cca ph as e mode. pwm ch a nnel s m a y b e gro u ped b y 2, 3 or 4 su ch th a t only one ch a nnel in a gro u p prod u ce s a p u l s e in a ny one period. the ph s [2-0] b it s m a y only b e written when the timer i s not a ctive, i.e. tr2 = 0. phs2 phs1 phs0 phase mode 000di sab led, a ll ch a nnel s a ctive 0012-ph as e o u tp u t on ch a nnel s a & b 0103-ph as e o u tp u t on ch a nnel s a, b & c 0114-ph as e o u tp u t on ch a nnel s a, b, c & d 100d ua l 2-ph as e o u tp u t on ch a nnel s a & b a nd c & d 101re s erved 110re s erved 111re s erved t2cm [1-0] timer 2 co u nt mode. t2cm1 t2cm0 count mode 00 s t a nd a rd timer 2 ( u p co u nt: ) 0 1 cle a r on rcap comp a re ( u p co u nt: ) 10d ua l- s lope with s ingle u pd a te ( u p-down co u nt: ) 11d ua l- s lope with do ub le u pd a te ( u p-down co u nt: ) t2oe timer 2 o u tp u t en ab le. when t2oe = 1 a nd c/t 2 = 0, the t2 pin will toggle a fter every timer 2 overflow. dcen timer 2 down co u nt en ab le. when timer 2 oper a te s in a u to-relo a d mode a nd exen2 = 1, s etting dcen = 1 will c aus e timer 2 to co u nt u p or down depending on the s t a te of t2ex. symbol function bottom max min top min top min min top min c a pt u re mode: time-o u t period 65536 o s cill a tor freq u ency ------------------------------------------------------ - tp s 1 + () =
63 3706c?micro?2/11 at89lp3240/6440 figure 12-1. timer 2 di a gr a m: c a pt u re mode 12.3 auto-reload mode timer 2 c a n b e progr a mmed to co u nt u p or down when config u red in it s 16- b it au to-relo a d mode. thi s fe a t u re i s invoked b y the dcen (down co u nter en ab le) b it loc a ted in the s fr t2mod ( s ee t ab le 12-4 ). upon re s et, the dcen b it i s s et to 0 s o th a t timer 2 will def au lt to co u nt u p. when dcen i s s et, timer 2 c a n co u nt u p or down, depending on the v a l u e of the t2ex pin. the overflow a nd relo a d v a l u e s depend on the timer 2 co u nt mode b it s , t2cm 1-0 in t2mod. a su mm a ry of the a u to-relo a d b eh a vior s i s li s ted in t ab le 12-5 . 12.3.1 up counter fig u re 12-2 s how s timer 2 au tom a tic a lly co u nting u p when dcen = 0 a nd t2cm 1-0 = 00b. in thi s mode timer 2 co u nt s u p to max a nd then s et s the tf2 b it u pon overflow. the overflow a l s o c aus e s the timer regi s ter s to b e relo a ded with bottom, the 16- b it v a l u e in rcap2h a nd rcap2l. if exen2 = 1, a 16- b it relo a d c a n b e triggered either b y a n overflow or b y a 1-to-0 tr a n- s ition a t extern a l inp u t t2ex. thi s tr a n s ition a l s o s et s the exf2 b it. both the tf2 a nd exf2 b it s c a n gener a te a n interr u pt. the timer 2 overflow r a te for thi s mode i s given in the following eq ua tion: timer 2 m a y a l s o b e config u red to co u nt from min to top in s te a d of bottom to max b y s et- ting t2cm 1-0 = 01b. in thi s mode timer 2 co u nt s u p to top, the 16- b it v a l u e in rcap2h a nd tps exf2 t2ex pin t2 pin tr2 exen2 c/t2 = 0 c/t2 = 1 capture overflow transition detector timer 2 interrupt rcap2h rcap2l tl2 th2 tf2 osc table 12-5. su mm a ry of a u to-relo a d mode s t2cm 1-0 dcen t2ex direction behavior 00 0 x up relo a d to bottom 00 1 0 down u nderflow to max 00 1 1 up overflow to bottom 01 0 x up relo a d to min 01 1 0 down u nderflow to top 01 1 1 up overflow to min 10 x x up-down a nd repe a t 11 x x up-down a nd repe a t bottom max u to-relo a d mode: dcen = 0, t2cm = 00b time-o u t period 65536 rcap2h rcap2l {,} ? o s cill a tor freq u ency ------------------------------------------------------------------------------ - tp s 1 + () =
64 3706c?micro?2/11 at89lp3240/6440 rcap2l a nd then overflow s . the overflow s et s tf2 a nd c aus e s the timer regi s ter s to b e relo a ded with min. if exen2 = 1, a 1-to-0 tr a n s ition on t2ex will cle a r the timer a nd s et exf2. the timer 2 overflow r a te for thi s mode i s given in the following eq ua tion: timer 2 co u nt mode 1 i s provided to su pport v a ri ab le preci s ion as ymmetric a l pwm in the cca. the v a l u e of top s tored in rcap2h a nd rcap2l i s do ub le- bu ffered su ch th a t a new top v a l u e t a ke s a ffect only a fter a n overflow. the b eh a vior of co u nt mode 0 ver sus co u nt mode 1 i s s hown in fig u re 12-3 . figure 12-2. timer 2 di a gr a m: a u to-relo a d mode (dcen = 0) figure 12-3. timer 2 w a veform: a u to-relo a d mode (dcen = 0) 12.3.2 up or down counter s etting dcen = 1 en ab le s timer 2 to co u nt u p or down, as s hown in fig u re 12-4 . in thi s mode, the t2ex pin control s the direction of the co u nt (if exen2 = 1). a logic 1 a t t2ex m a ke s timer 2 co u nt u p. when t2cm 1-0 = 00b, the timer will overflow a t max a nd s et the tf2 b it. thi s overflow a l s o c aus e s bottom, the 16- b it v a l u e in rcap2h a nd rcap2l, to b e relo a ded into the timer a u to-relo a d mode: dcen = 0, t2cm = 01b time-o u t period rcap2h rcap2l {,} 1 + o s cill a tor freq u ency ----------------------------------------------------------------- - tp s 1 + () = tps tl2 th2 max min bottom t2cm 1-0 = 00b, dcen = 0 max min top t2cm 1-0 = 01b, dcen = 0 tf2 s et tf2 s et
65 3706c?micro?2/11 at89lp3240/6440 regi s ter s , th2 a nd tl2, re s pectively. a logic 0 a t t2ex m a ke s timer 2 co u nt down. the timer u nderflow s when th2 a nd tl2 eq ua l bottom, the 16- b it v a l u e s tored in rcap2h a nd rcap2l. the u nderflow s et s the tf2 b it a nd c aus e s max to b e relo a ded into the timer regi s - ter s . the exf2 b it toggle s whenever timer 2 overflow s or u nderflow s a nd c a n b e us ed as a 17th b it of re s ol u tion. in thi s oper a ting mode, exf2 doe s not fl a g a n interr u pt. when t2ex = 1 a nd t2cm 1-0 = 01b, the timer will overflow a t top a nd s et the tf2 b it. thi s overflow a l s o c aus e s min to b e relo a ded into the timer regi s ter s . a logic 0 a t t2ex m a ke s timer 2 co u nt down. the timer u nderflow s when th2 a nd tl2 eq ua l min. the u nderflow s et s the tf2 b it a nd c aus e s top to b e relo a ded into the timer regi s ter s . the b eh a vior of co u nt mode 0 ver- sus co u nt mode 0 when dcen i s en ab led i s s hown in fig u re 12-6 . figure 12-4. timer 2 di a gr a m: a u to-relo a d mode (t2cm 1-0 = 00b, dcen = 1) the timer overflow/ u nderflow r a te for u p-down co u nting mode i s the sa me as for u p co u nting mode, provided th a t the co u nt direction doe s not ch a nge. ch a nge s to the co u nt direction m a y re su lt in longer or s horter period s b etween time-o u t s . figure 12-5. timer 2 di a gr a m: a u to-relo a d mode (t2cm 1-0 = 01b, dcen = 1) tps tps
66 3706c?micro?2/11 at89lp3240/6440 figure 12-6. timer 2 w a veform: a u to-relo a d mode (dcen = 1) 12.3.3 dual slope counter when timer 2 a u to-relo a d mode us e s co u nt mode 2 (t2cm 1-0 = 10b) or co u nt mode 3 (t2cm 1-0 = 11b), the timer oper a te s in a d ua l s lope f as hion. the timer co u nt s u p from min to top a nd then co u nt s down from top to min, following a sa wtooth w a veform as s hown in fig- u re 12-7 . the exf2 b it i s s et/cle a red b y h a rdw a re to reflect the c u rrent co u nt direction (up = 0 a nd down = 1). the v a l u e of top s tored in rcap2h a nd rcap2l i s do ub le- bu ffered su ch th a t a new top v a l u e t a ke s a ffect only a fter a n u nderflow. the only difference b etween mode 2 a nd mode 3 i s when the interr u pt fl a g i s s et. in mode 2 tf2 i s s et once per co u nt period when the timer u nderflow s a t min. in mode 3 tf2 i s s et twice per co u nt period, once when the timer over- flow s a t top a nd once when the timer u nderflow s a t min. the interr u pt s ervice ro u tine c a n check the exf2 b it to determine if tf2 w as s et a t top or min. the s e co u nt mode s a re provided to su pport v a ri ab le preci s ion s ymmetric a l pwm in the cca. dcen h as no effect when us ing d ua l s lope oper a tion. the timer 2 overflow r a te for thi s mode i s given in the following eq ua tion: max min bottom t2cm 1-0 = 00b, dcen = 1 max min top t2cm 1-0 = 01b, dcen = 1 t2ex tf2 s et tf2 s et exf2 a u to-relo a d mode: dcen = 0, t2cm = 10b time-o u t period rcap2h rcap2l {,} 2 o s cill a tor freq u ency ------------------------------------------------------------------ - tp s 1 + () =
67 3706c?micro?2/11 at89lp3240/6440 figure 12-7. timer 2 w a veform: d ua l s lope mode s 12.4 baud rate generator timer 2 i s s elected as the bau d r a te gener a tor b y s etting tclk a nd/or rclk in t2con ( t ab le 12-3 ). note th a t the bau d r a te s for tr a n s mit a nd receive c a n b e different if timer 2 i s us ed for the receiver or tr a n s mitter a nd timer 1 i s us ed for the other f u nction. s etting rclk a nd/or tclk p u t s timer 2 into it s bau d r a te gener a tor mode, as s hown in fig u re 12- 8 . the bau d r a te gener a tor mode i s s imil a r to the au to-relo a d mode, in th a t a rollover in th2 c aus e s the timer 2 regi s ter s to b e relo a ded with the 16- b it v a l u e in regi s ter s rcap2h a nd rcap2l, which a re pre s et b y s oftw a re. the bau d r a te s in uart mode s 1 a nd 3 a re determined b y timer 2? s overflow r a te a ccording to the following eq ua tion. the timer c a n b e config u red for either timer or co u nter oper a tion. in mo s t a pplic a tion s , it i s con- fig u red for timer oper a tion (cp/t2 = 0). the bau d r a te form u l as a re given b elow. where (rcap2h, rcap2l) i s the content of rcap2h a nd rcap2l t a ken as a 16- b it u n s igned integer. timer 2 as a bau d r a te gener a tor i s s hown in fig u re 12- 8 . thi s fig u re i s v a lid only if rclk or tclk = 1 in t2con. note th a t a rollover in th2 doe s not s et tf2 a nd will not gener a te a n inter- r u pt. note too, th a t if exen2 i s s et, a 1-to-0 tr a n s ition in t2ex will s et exf2 bu t will not c aus e a relo a d from (rcap2h, rcap2l) to (th2, tl2). th us when timer 2 i s in us e as a bau d r a te gen- max min top t2cm 1-0 = 10b max min top tf2 s et tf2 s et t2cm 1-0 = 11b exf2 mode s 1 a nd 3 b au d r a te s timer 2 overflow r a te 16 ----------------------------------------------------------- - = t2cm = 00b mode s 1, 3 b au d r a te o s cill a tor freq u ency 16 tp s 1 + () 65536 rcap2h,rcap2l () ? [] ------------------------------------------------------------------------------------------------------------------------------- - - = t2cm = 01b mode s 1, 3 b au d r a te o s cill a tor freq u ency 16 tp s 1 + () rcap2h rcap2l (,) 1 + [] ------------------------------------------------------------------------------------------------------------------ - =
68 3706c?micro?2/11 at89lp3240/6440 er a tor, t2ex c a n b e us ed as a n extr a extern a l interr u pt. al s o note th a t the b au d r a te a nd freq u ency gener a tor mode s m a y b e us ed s im u lt a neo us ly. figure 12-8. timer 2 in b au d r a te gener a tor mode 12.5 frequency generator (p rogrammable clock out) timer 2 c a n gener a te a 50% d u ty cycle clock on t2 (p1.0), as s hown in fig u re 12-9 . thi s pin, b e s ide s b eing a reg u l a r i/o pin, h as two a ltern a te f u nction s . it c a n b e progr a mmed to inp u t the extern a l clock for timer/co u nter 2 or to toggle it s o u tp u t a t every timer overflow. to config u re the timer/co u nter 2 as a clock gener a tor, b it c/t2 (t2con.1) m us t b e cle a red a nd b it t2oe (t2mod.1) m us t b e s et. bit tr2 (t2con.2) s t a rt s a nd s top s the timer. the clock-o u t freq u ency depend s on the o s cill a tor freq u ency a nd the relo a d v a l u e of timer 2 c a pt u re regi s ter s (rcap2h, rcap2l), as s hown in the following eq ua tion s . in the freq u ency gener a tor mode, timer 2 roll-over s will not gener a te a n interr u pt. thi s b eh a vior i s s imil a r to when timer 2 i s us ed as a bau d-r a te gener a tor. it i s po ss i b le to us e timer 2 as a bau d-r a te gener a tor a nd a clock gener a tor s im u lt a neo us ly. note, however, th a t the bau d-r a te a nd clock-o u t freq u encie s c a nnot b e determined independently from one a nother s ince they b oth us e rcap2h a nd rcap2l. tps smod1 rclk tclk rx clock tx clock t2ex pin t2 pin tr2 "1" "1" "1" "0" "0" "0" timer 1 overflow timer 2 interrupt 2 16 16 rcap2h rcap2l tl2 th2 c/t2 = 0 c/t2 = 1 exf2 transition detector exen2 osc t2cm = 00b clock o u t freq u ency o s cill a tor freq u ency 2 65536 rcap2h,rcap2l () ? [] ------------------------------------------------------------------------------------------- - 1 tp s 1 + -------------------- - = t2cm = 01b clock o u t freq u ency o s cill a tor freq u ency 2 rcap2h,rcap2l () 1 + [] ------------------------------------------------------------------------------ - 1 tp s 1 + -------------------- - =
69 3706c?micro?2/11 at89lp3240/6440 figure 12-9. timer 2 in clock-o u t mode 13. compare/capture array the at 8 9lp3240/6440 incl u de s a fo u r ch a nnel comp a re/c a pt u re arr a y (cca) th a t perform s a v a riety of timing oper a tion s incl u ding inp u t event c a pt u re, o u tp u t comp a re w a veform gener a tion a nd p u l s e width mod u l a tion (pwm). timer 2 s erve s as the time bas e for the fo u r 16- b it com- p a re/c a pt u re mod u le s . the cca h as the following fe a t u re s : ?fo u r 16- b it comp a re/c a pt u re ch a nnel s ? common time bas e provided b y timer 2 ? s elect ab le extern a l a nd intern a l c a pt u re event s incl u ding pin ch a nge, timer overflow a nd comp a r a tor o u tp u t ch a nge ? s ymmetric/a s ymmetric pwm with s elect ab le pol a rity ?m u lti-ph as ic pwm o u tp u t s ? one interr u pt fl a g per ch a nnel with a common interr u pt vector the b lock di a gr a m of the cca i s given in fig u re 13-1 . e a ch ch a nnel con s i s t s of a n 8 - b it control regi s ter a nd a 16- b it d a t a regi s ter. the ch a nnel regi s ter s a re not directly a cce ss i b le. the cca a ddre ss regi s ter t2cca provide s a n index into the a rr a y. the control, d a t a low a nd d a t a high b yte s of the c u rrently indexed ch a nnel a re a cce ss ed thro u gh the t2ccc, t2ccl a nd t2cch regi s ter s re s pectively. e a ch ch a nnel c a n b e individ ua lly config u red for c a pt u re or comp a re mode. c a pt u re mode i s the def au lt s etting. d u ring c a pt u re mode the c u rrent v a l u e of the time bas e i s copied into the ch a n- nel? s d a t a regi s ter when the s pecified extern a l or intern a l event occ u r s . an interr u pt fl a g i s s et a t the sa me time a nd the time bas e m a y b e option a lly cle a red. to en ab le comp a re mode, the ccm x b it in the ch a nnel? s control regi s ter (ccc x ) s ho u ld b e s et to 1. in comp a re mode a n inter- r u pt fl a g i s s et a nd a n o u tp u t pin i s option a lly toggled when the v a l u e of the time bas e m a tche s the v a l u e of the ch a nnel? s d a t a regi s ter. the time bas e m a y a l s o b e option a lly cle a red on a com- p a re m a tch. timer 2 m us t b e r u nning (tr2 = 1) in order to perform c a pt u re s or comp a re s with the cca. however, when tr2 = 0 the extern a l c a pt u re event s will s till s et their ass oci a ted fl a g s a nd m a y b e us ed as a ddition a l extern a l interr u pt s . osc t2ex pin t2 pin tr2 timer 2 interrupt rcap2h rcap2l tl2 th2 c/t2 exf2 transition detector exen2 tps 2 t2oe
70 3706c?micro?2/11 at89lp3240/6440 figure 13-1. comp a re/c a pt u re arr a y block di a gr a m 13.1 cca registers the comp a re/c a pt u re arr a y h as five s peci a l f u nction regi s ter s : t2cca, t2ccc, t2ccl, t2cch a nd t2ccf. the t2ccf regi s ter cont a in s the interr u pt fl a g s for e a ch cca ch a nnel. the cca interr u pt i s a logic or of the b it s in t2ccf. the fl a g s a re s et b y h a rdw a re when a com- p a re/c a pt u re event occ u r s on the relev a nt ch a nnel a nd m us t b e cle a red b y s oftw a re. the t2ccf b it s will only gener a te a n interr u pt when the ecc b it (ie2.1) i s s et a nd the cien x b it in the ass oci a ted ch a nnel? s ccc x regi s ter i s s et. the t2ccc, t2ccl a nd t2cch regi s ter loc a tion s a re not tr u e s fr s . the s e loc a tion s repre s ent a cce ss point s to the content s of the a rr a y. write s /re a d s to/from the t2ccc, t2ccl a nd t2cch loc a tion s will a cce ss the control, d a t a low a nd d a t a high b yte s of the cca ch a nnel c u rrently s elected b y the index in t2cca. ch a nnel s c u rrently not indexed b y t2cca a re not a cce ss i b le. when writing to t2cch, the v a l u e i s s tored in a s h a dow regi s ter. when t2ccl i s written, the 16- b it v a l u e formed b y the content s of t2ccl a nd the t2cch s h a dow i s written into the a rr a y. therefore, t2cch m us t b e written prior to writing t2ccl. all fo u r ch a nnel s us e the sa me t2cch s h a dow regi s ter. if the v a l u e of t2cch rem a in s con s t a nt for m u ltiple write s , there i s no need to u pd a te t2cch b etween t2ccl write s . every write to t2ccl will us e the l as t v a l u e of t2cch for the u pper d a t a b yte. it i s not po ss i b le to write to the d a t a regi s ter of a ch a nnel config- u red for c a pt u re mode. the config u r a tion b it s for e a ch ch a nnel a re s tored in the ccc x regi s ter s a cce ss i b le thro u gh t2ccc. s ee t ab le 13-5 on p a ge 74 for a de s cription of the ccc x regi s ter. o s c (p1.0) t2 tr2 tl2 timer 2 interr u pt c/t2 = 0 c/t2 =1 th2 tf2 rcap2l rcap2h tp s ccal ccah ccca ccbl ccbh cccb cccl ccch cccc ccdl ccdh cccd t2ccf cca interr u pt cca (p2.0) ccb (p2.1) ccc (p2.2) ccd (p2.3) t2ccc t2ccl t2cch t2cca
71 3706c?micro?2/11 at89lp3240/6440 note: all write s /re a d s to/from t2cch will a cce ss ch a nnel x as c u rrently s elected b y t2cca.the d a t a regi s ter s for the rem a ining u n s elected ch a nnel s a re not a cce ss i b le. note: all write s /re a d s to/from t2ccl will a cce ss ch a nnel x as c u rrently s elected b y t2cca.the d a t a regi s ter s for the rem a ining u n s elected ch a nnel s a re not a cce ss i b le. table 13-1. t2cca ? timer/co u nter 2 comp a re/c a pt u re addre ss t2cca addre ss = 0d1h re s et v a l u e = xxxx xx00b not bit addre ssab le ??????t2cca.1t2cca.0 bit76543210 symbol function t2cca [1-0] comp a re/c a pt u re addre ss . s elect s which cca ch a nnel i s c u rrently a cce ss i b le thro u gh the t2cch, t2ccl a nd t2ccc regi s ter s . only one ch a nnel m a y b e a cce ss ed a t a time. t2cca1 t2cca0 channel 0 0 a ? t2cch, t2ccl a nd t2ccc a cce ss d a t a a nd control for ch a nnel a 0 1 b ? t2cch, t2ccl a nd t2ccc a cce ss d a t a a nd control for ch a nnel b 1 0 c ? t2cch, t2ccl a nd t2ccc a cce ss d a t a a nd control for ch a nnel c 1 1 d ? t2cch, t2ccl a nd t2ccc a cce ss d a t a a nd control for ch a nnel d table 13-2. t2cch ? timer/co u nter 2 comp a re/c a pt u re d a t a high t2cch addre ss = 0d2h re s et v a l u e = 0000 0000b not bit addre ssab le t2ccd.15 t2ccd.14 t2ccd.13 t2ccd.12 t2ccd.11 t2ccd.10 t2ccd.9 t2ccd. 8 bit76543210 symbol function t2ccd [15- 8 ] comp a re/c a pt u re d a t a (high byte). re a d s from t2cch will ret u rn the high b yte from the cca ch a nnel c u rrently s elected b y t2cca. the high b yte of the s elected cca ch a nnel will b e u pd a ted with the content s of t2cch when t2ccl i s written. when writing m u ltiple ch a nnel s with the sa me high b yte, t2cch need not b e u pd a ted b etween write s to t2ccl. table 13-3. t2ccl ? timer/co u nter 2 comp a re/c a pt u re d a t a low t2ccc addre ss = 0d3h re s et v a l u e = 0000 0000b not bit addre ssab le t2ccd.7 t2ccd.6 t2ccd.5 t2ccd.4 t2ccd.3 t2ccd.2 t2ccd.1 t2ccd.0 bit76543210 symbol function t2ccd [7-0] comp a re/c a pt u re d a t a (low byte). re a d s from t2ccl will ret u rn the low b yte from the cca ch a nnel c u rrently s elected b y t2cca. write s to t2ccl will u pd a te the s elected cca ch a nnel with the 16- b it content s of t2cch a nd t2ccl.
72 3706c?micro?2/11 at89lp3240/6440 13.2 input capture mode the comp a re/c a pt u re arr a y provide s a v a riety of c a pt u re mode s su it ab le for time- s t a mping event s or performing me asu rement s of p u l s e width, freq u ency, s lope, etc. cca ch a nnel s a re config u red for c a pt u re mode b y cle a ring the ccm x b it in the ass oci a ted ccc x regi s ter to 0. e a ch time a c a pt u re event occ u r s , the content s of timer 2 (th2 a nd tl2) a re tr a n s ferred to the 16- b it d a t a regi s ter of the corre s ponding ch a nnel, a nd the ch a nnel? s interr u pt fl a g ccf x i s s et in t2ccf. option a lly, the c a pt u re event m a y a l s o cle a r timer 2 to 0000h b y s etting the ctc x b it in ccc x . the c a pt u re event i s defined b y the c x m 2-0 b it s in ccc x a nd m a y b e either extern a lly or intern a lly gener a ted. a di a gr a m of a cca ch a nnel in c a pt u re mode i s s hown in fig u re 13-2 . figure 13-2. cca c a pt u re mode di a gr a m e a ch cca ch a nnel h as a n ass oci a ted extern a l c a pt u re inp u t pin: cca (p2.0), ccb (p2.1), ccc (p2.2) a nd ccd (p2.3). extern a l c a pt u re event s a re a lw a y s edge-triggered a nd c a n b e s elected table 13-4. t2ccf ? timer/co u nter 2 comp a re/c a pt u re fl a g s t2ccf addre ss = 0d5h re s et v a l u e = xxxx 0000b not bit addre ssab le ? ? ? ? ccfd ccfc ccfb ccfa bit76543210 symbol function ccfd ch a nnel d comp a re/c a pt u re interr u pt fl a g. s et b y a comp a re/c a pt u re event on ch a nnel d. m us t b e cle a red b y s oftw a re. ccfd will gener a te a n interr u pt when ciend = 1 a nd ecc = 1. ccfc ch a nnel c comp a re/c a pt u re interr u pt fl a g. s et b y a comp a re/c a pt u re event on ch a nnel c. m us t b e cle a red b y s oftw a re. ccfc will gener a te a n interr u pt when cienc = 1 a nd ecc = 1. ccfb ch a nnel b comp a re/c a pt u re interr u pt fl a g. s et b y a comp a re/c a pt u re event on ch a nnel b. m us t b e cle a red b y s oftw a re. ccfb will gener a te a n interr u pt when cienb = 1 a nd ecc = 1. ccfa ch a nnel a comp a re/c a pt u re interr u pt fl a g. s et b y a comp a re/c a pt u re event on ch a nnel a. m us t b e cle a red b y s oftw a re. ccfa will gener a te a n interr u pt when ciena = 1 a nd ecc = 1. tl2 th2 ccxl ccxh cccx interr u pt (p2.x) ccx t2ccc t2ccl t2cch 0 1 2 3 4 5 6 7 ?0? timer 0 overflow timer 1 overflow comp a r a tor a comp a r a tor b 00h 00h ctcx ccfx cienx cxm 2-0
73 3706c?micro?2/11 at89lp3240/6440 to occ u r a t a neg a tive edge, po s itive edge, or b oth (toggle). c a pt u re inp u t s a re sa mpled every clock cycle a nd a new v a l u e m us t b e held for a t le as t 2 clock cycle s to b e correctly sa mpled b y the device. the m a xim u m a chiev ab le c a pt u re r a te will b e determined b y how f as t the s oftw a re c a n retrieve the c a pt u red d a t a . there i s no protection a g a in s t c a pt u re event s overr u nning the d a t a regi s ter. c a pt u re event s m a y a l s o b e triggered intern a lly b y the overflow s of timer 0 or timer 1, or b y a n event from the d ua l a n a log comp a r a tor s . any comp a r a tor event which c a n gener a te a comp a r a - tor interr u pt m a y a l s o b e us ed as a c a pt u re event. however, timer 2 s ho u ld not b e s elected as the comp a r a tor clock s o u rce when us ing the comp a r a tor as the c a pt u re trigger. when the dac o u tp u t i s en ab led on p2.2 a nd p2.3, ch a nnel s c a nd d c a nnot us e their extern a l pin c a pt u re mode s . however, tho s e ch a nnel s m a y s till us e the timer or comp a r a tor trigger s to c a pt u re d a t a . the sa me a pplie s for a ll fo u r ch a nnel s when port 2 i s us ed for the extern a l mem- ory interf a ce. 13.2.1 timer 2 operation for capture mode c a pt u re ch a nnel s a re intended to work with timer 2 in c a pt u re mode cp/rl2 =1. c a pt u re s c a n s till occ u r when timer 2 oper a te s in other mode s ; however, the f u ll 16- b it co u nt r a nge m a y not b e a v a il ab le. the tf2 fl a g c a n b e us ed to determine if the timer overflowed b efore the c a pt u re occ u rred. if the timer i s oper a ting in d ua l- s lope mode (cp/rl2 =0, t2cm 1-0 =1xb), the co u nt direction (up = 0 a nd down = 1) a t the time of the event will b e c a pt u red into the ch a nnel? s cdir x b it in ccc x . ctc x m us t b e cle a red to 0 for a ll ch a nnel s if timer 2 i s oper a ting in b au d r a te mode or error s m a y occ u r in the s eri a l comm u nic a tion.
74 3706c?micro?2/11 at89lp3240/6440 note s : 1. all write s /re a d s to/from t2ccc will a cce ss ch a nnel x as c u rrently s elected b y t2cca.the control regi s ter s for the rem a in- ing u n s elected ch a nnel s a re not a cce ss i b le. 2. an a log comp a r a tor a event s a re determined b y the cma 2-0 b it s in ac s ra. s ee t ab le 19-1 on p a ge 130 . 3. an a log comp a r a tor b event s a re determined b y the cmb 2-0 b it s in ac s rb. s ee t ab le 19-2 on p a ge 131 . 4. a s ymmetric a l ver sus s ymmetric a l pwm i s determined b y the timer 2 co u nt mode. s ee s ection 13.4 on p a ge 77 . table 13-5. t2ccc ? timer/co u nter 2 comp a re/c a pt u re control t2ccc addre ss = 0d4h re s et v a l u e = 00x0 0000b not bit addre ssab le cien x cdir x ?ctc x ccm x c x m2 c x m1 c x m0 bit76543210 symbol function cien x ch a nnel x interr u pt en ab le. when s et, ch a nnel x ? s interr u pt fl a g, ccf x in t2ccf, will gener a te a n interr u pt when ecc = 1. cle a r to di sab le interr u pt s from ch a nnel x . cdir x ch a nnel x c a pt u re direction. in d ua l- s lope mode s , a comp a re/c a pt u re event on ch a nnel x will s tore the c u rrent co u nt direction into cdir x . up-co u nting = 0 a nd down-co u nting = 1. modifying thi s b it h as no effect. ctc x cle a r timer on comp a re/c a pt u re of ch a nnel x . when s et, the timer 2 regi s ter s tl2 a nd th2 will b e cle a red b y a comp a re/c a pt u re event on ch a nnel x . when cle a red, timer 2 i s u n a ffected b y ch a nnel x event s . ccm x ch a nnel x comp a re/c a pt u re mode. when ccm x = 1, ch a nnel x oper a te s in comp a re mode. when ccm x = 0, ch a nnel x oper a te s in c a pt u re mode. cxm[2-0] ch a nnel x mode. s elect s the o u tp u t/inp u t event s for comp a re/c a pt u re ch a nnel x . c x m2 c x m1 c x m0 capture event (ccm x = 0) 000di sab led 001trigger on neg a tive edge of cc x pin 010trigger on po s itive edge of cc x pin 011trigger on either edge of cc x pin 100trigger on timer 0 overflow 101trigger on timer 1 overflow 110trigger on an a log comp a r a tor a event (2) 111trigger on an a log comp a r a tor b event (3) c x m2 c x m1 c x m0 compare action (ccm x = 1) 000o u tp u t di sab led (interr u pt only) 001 s et cc x pin on comp a re m a tch 010cle a r cc x pin on comp a re m a tch 011toggle cc x pin on comp a re m a tch 100inverting p u l s e width mod u l a tion (4) 101non-inverting p u l s e width mod u l a tion (4) 110re s erved 111re s erved
75 3706c?micro?2/11 at89lp3240/6440 13.3 output compare mode the comp a re/c a pt u re arr a y provide s a v a riety of comp a re mode s su it ab le for event timing or w a veform gener a tion. cca ch a nnel s a re config u red for comp a re mode b y s etting the ccm x b it in the ass oci a ted ccc x regi s ter to 1. a comp a re event occ u r s when the 16- b it content s of a ch a nnel? s d a t a regi s ter m a tch the content s of timer 2 (th2 a nd tl2). the comp a re event a l s o s et s the ch a nnel? s interr u pt fl a g ccf x in t2ccf a nd m a y option a lly cle a r timer 2 to 0000h if the ctc x b it in ccc x i s s et. a di a gr a m of a cca ch a nnel in comp a re mode i s s hown in fig u re 13-3 . figure 13-3. cca comp a re mode di a gr a m 13.3.1 waveform generation e a ch cca ch a nnel h as a n ass oci a ted extern a l comp a re o u tp u t pin: cca (p2.0), ccb (p2.1), ccc (p2.2) a nd ccd (p2.3). the c x m 2-0 b it s in ccc x determine wh a t a ction i s t a ken when a comp a re event occ u r s . the o u tp u t pin m a y b e s et to 1, cle a red to 0 or toggled. o u tp u t a ction s t a ke pl a ce even if the interr u pt i s di sab led; however, the ass oci a ted i/o pin m us t b e s et to the de s ired o u tp u t mode b efore the comp a re event occ u r s . the s t a te of the comp a re o u tp u t s a re ini- ti a lized to 1 b y re s et. ch a nnel s c a nd d c a nnot us e their o u tp u t pin when the dac i s en ab led. the s e ch a nnel s m a y s till b e us ed to gener a te interr u pt s or to cle a r the time bas e. the sa me a pplie s to a ll fo u r ch a nnel s when port 2 i s us ed for the extern a l memory interf a ce. m u ltiple comp a re event s per ch a nnel c a n occ u r within a s ingle time period, provided th a t the s oftw a re h as time to u pd a te the comp a re v a l u e b efore the timer re a che s the next comp a re point. in thi s c as e other interr u pt s s ho u ld b e di sab led or the cca interr u pt given a higher priority in order to en su re th a t the interr u pt i s s erviced in time. a wide r a nge of w a veform gener a tion config u r a tion s a re po ss i b le us ing the v a rio us oper a ting mode s of timer 2 a nd the cca. s ome ex a mple config u r a tion s a re det a iled b elow. p u l s e width mod u l a tion i s a s peci a l c as e of o u tp u t comp a re. s ee s ection 13.4 on p a ge 77 for more det a il s of pwm oper a tion. tl2 th2 ccxl ccxh cccx interr u pt ccx (p2.x) t2ccc t2ccl s h a dow 00h 00h ctcx ccfx cienx cxm 2-0 = t2cch
76 3706c?micro?2/11 at89lp3240/6440 13.3.1.1 normal mode the s imple s t w a veform mode i s when cp/rl2 =0 a nd t2cm1-0 = 01b. in thi s mode the fre- q u ency of the o u tp u t i s determined b y the top v a l u e s tored in rcap2l a nd rcap2h a nd o u tp u t edge s occ u r a t fr a ction s of the timer period. fig u re 13-4 s how s a n ex a mple of o u tp u tting two w a veform s of the sa me freq u ency bu t different ph as e b y us ing the toggle on m a tch a ction. more complex w a veform s a re a chieved b y ch a nging the top v a l u e a nd the comp a re v a l u e s more freq u ently. figure 13-4. norm a l mode w a veform ex a mple 13.3.1.2 clear-timer-on-compare mode cle a r-timer-on-comp a re (ctc) mode occ u r s when the ctc x b it of a comp a re ch a nnel i s s et to one. ctc mode work s b e s t when timer 2 i s in c a pt u re mode (cp/rl2 =1) to a llow the f u ll r a nge of comp a re v a l u e s . in ctc mode the comp a re v a l u e define s the interv a l b etween o u tp u t event s b ec aus e the timer i s cle a red a fter every comp a re m a tch. fig u re 13-5 s how s a n ex a mple w a ve- form us ing the toggle on m a tch a ction in ctc mode. figure 13-5. ctc mode w a veform ex a mple 13.3.1.3 dual-slope mode the d ua l- s lope mode occ u r s when cp/rl2 =0 a nd t2cm 1-0 = 1xb. in thi s mode the freq u ency of the o u tp u t i s determined b y the top v a l u e s tored in rcap2l a nd rcap2h a nd o u tp u t edge s occ u r a t fr a ction s of the timer period on b oth the u p a nd down co u nt. fig u re 13-6 s how s a n ex a mple of o u tp u tting two s ymmetric a l w a veform s us ing the toggle on m a tch a ction. more com- plex w a veform s a re a chieved b y ch a nging the top v a l u e a nd the comp a re v a l u e s more freq u ently. {rcap2h,rca2l} cp/rl2 = 0, t2cm 1-0 = 01b, dcen = 0 cca {ccah,ccal} {ccbh,ccbl} ccb cp/rl2 = 1 cca {ccah,ccal}
77 3706c?micro?2/11 at89lp3240/6440 figure 13-6. d ua l- s lope w a veform ex a mple 13.3.2 timer 2 operation for compare mode comp a re ch a nnel s will work with a ny timer 2 oper a ting mode. the f u ll 16- b it comp a re r a nge m a y not b e a v a il ab le in a ll mode s . in order for a comp a re o u tp u t a ction to t a ke pl a ce, the com- p a re v a l u e s m us t b e within the co u nting r a nge of timer 2. ctc x m us t b e cle a red to 0 for a ll ch a nnel s if timer 2 i s oper a ting in b au d r a te mode or error s m a y occ u r in the s eri a l comm u nic a tion. 13.4 pulse width modulation mode in p u l s e width mod u l a tion (pwm) mode, a comp a re ch a nnel c a n o u tp u t a s q ua re w a ve with pro- gr a mm ab le freq u ency a nd d u ty cycle. s etting ccmx = 1 a nd cxm 2-0 = 10xb en ab le s pwm mode. pwm mode i s s imil a r to o u tp u t comp a re mode except th a t the comp a re v a l u e i s do ub le- bu ffered. a di a gr a m of a cca ch a nnel in pwm mode i s s hown in fig u re 13-7 . the pwm pol a rity i s s elect ab le b etween inverting a nd non-inverting mode s . pwm i s intended for us e with timer 2 in a u to-relo a d mode (cp/rl2 =0, dcen=0) us ing co u nt mode s 1, 2 or 3. the pwm c a n oper- a te in as ymmetric (edge- a ligned) or s ymmetric (center- a ligned) mode depending on the t2cm s election. the cca pwm h as v a ri ab le preci s ion from 2 to 16 b it s . a tr a de-off b etween freq u ency a nd preci s ion i s m a de b y ch a nging the top v a l u e of the timer. the cca pwm a lw a y s us e s the gre a te s t preci s ion a llow ab le for the s elected o u tp u t freq u ency, as comp a red to timer 0 a nd 1 who s e pwm s a re fixed a t 8 - b it preci s ion reg a rdle ss of freq u ency. figure 13-7. cca pwm mode di a gr a m {rcap2h,rca2l} cp/rl2 = 0, t2cm 1-0 = 10b, dcen = 0 cca {ccah,ccal} {ccbh,ccbl} ccb tl2 th2 ccxl ccxh cccx interr u pt ccx (p2.x) t2ccc t2ccl s h a dow ccfx cienx cxm 2-0 = t2cch s h a dow s h a dow
78 3706c?micro?2/11 at89lp3240/6440 13.4.1 asymmetrical pwm for a s ymmetric a l pwm, timer 2 s ho u ld b e config u red for a u to-relo a d mode a nd co u nt mode 1 (cp/rl2 =0, dcen=0, t2cm1-0 = 01b). a s ymmetric a l pwm us e s s ingle s lope oper a tion as s hown in fig u re 13- 8 . the timer co u nt s u p from bottom to top a nd then re s t a rt s from bot- tom. in non-inverting mode, the o u tp u t cc x i s s et on the comp a re m a tch b etween timer 2 (tl2, th2) a nd the ch a nnel d a t a regi s ter (cc x l, cc x h), a nd cle a red a t bottom. in inverting mode, the o u tp u t cc x i s cle a red on the comp a re m a tch b etween timer 2 a nd the d a t a regi s ter, a nd s et a t bottom. the re su lting as ymmetric a l o u tp u t w a veform i s left-edge a ligned. the top v a l u e in rcap2l a nd rcap2h i s do ub le bu ffered su ch th a t the o u tp u t freq u ency i s only u pd a ted a t the top to bottom overflow. the ch a nnel d a t a regi s ter (cc x l, cc x h) i s a l s o do ub le- bu ffered su ch th a t the d u ty cycle i s only u pd a ted a t the top to bottom overflow to pre- vent glitche s . the o u tp u t freq u ency a nd d u ty cycle for as ymmetric a l pwm a re given b y the following eq ua tion s : the extreme comp a re v a l u e s repre s ent s peci a l c as e s when gener a ting a pwm w a veform. if the comp a re v a l u e i s s et eq ua l to (or gre a ter th a n) top, the o u tp u t will rem a in low or high for non- inverting a nd inverting mode s , re s pectively. if the comp a re v a l u e i s s et to bottom (0000h), the o u tp u t will rem a in high or low for non-inverting a nd inverting mode s , re s pectively. figure 13-8. a s ymmetric a l (edge-aligned) pwm 13.4.2 symmetrical pwm for s ymmetric a l pwm, timer 2 s ho u ld b e config u red for a u to-relo a d mode a nd co u nt mode 2 or 3 (cp/rl2 = 0, dcen = 0, t2cm1-0 =1xb). s ymmetric a l pwm us e s d ua l- s lope oper a tion as s hown in fig u re 13-9 . the timer co u nt s u p from min to top a nd then co u nt s down from top to min. the timer i s eq ua l to top for ex a ctly one clock cycle. in non-inverting mode, the o u tp u t cc x i s cle a red on the u p-co u nt comp a re m a tch b etween timer 2 (tl2, th2) a nd the ch a nnel d a t a regi s ter (cc x l, cc x h), a nd s et a t the down-co u nt comp a re m a tch. in inverting mode, the o u tp u t cc x i s s et on the u p-co u nt comp a re m a tch b etween timer 2 a nd the d a t a regi s ter, a nd cle a red a t the down-co u nt comp a re m a tch. the re su lting s ymmetric a l pwm o u tp u t w a veform i s f out o s cill a tor freq u ency rcap2h rcap2l {,} 1 + ---------------------------------------------------------------- 1 tp s 1 + -------------------- - = inverting: d u ty cycle 100% ccxh ccxl {,} rcap2h rcap2l {,} 1 + ---------------------------------------------------------------- = non-inverting: d u ty cycle 100% rcap2h rcap2l {,} ccxh ccxl {,} ? 1 + rcap2h rcap2l {,} 1 + ------------------------------------------------------------------------------------------------------------ - = {rcap2h,rca2l} cp/rl2 = 0, t2cm 1-0 = 01b, dcen = 0 inverted {ccxh,ccxl} non-inverted ccx
79 3706c?micro?2/11 at89lp3240/6440 center- a ligned a ro u nd the timer eq ua l to top point. s ymmetric a l pwm m a y b e us ed to gener a te non-overl a pping w a veform s . the top v a l u e in rcap2l a nd rcap2h i s do ub le bu ffered su ch th a t the o u tp u t freq u ency i s only u pd a ted a t the u nderflow. the ch a nnel d a t a regi s ter (cc x l, cc x h) i s a l s o do ub le- bu ffered to prevent glitche s . the o u tp u t freq u ency a nd d u ty cycle for s ymmetric a l pwm a re given b y the following eq ua tion s : the extreme comp a re v a l u e s repre s ent s peci a l c as e s when gener a ting a pwm w a veform. if the comp a re v a l u e i s s et eq ua l to (or gre a ter th a n) top, the o u tp u t will rem a in high or low for non- inverting a nd inverting mode s , re s pectively. if the comp a re v a l u e i s s et to min (0000h), the o u t- p u t will rem a in low or high for non-inverting a nd inverting mode s , re s pectively. figure 13-9. non-overl a pping w a veform s u s ing s ymmetric a l pwm 13.4.2.1 phase and frequency correct pwm when t2cm 1-0 = 10b the s ymmetric a l pwm oper a te s in ph as e a nd freq u ency correct mode. in thi s mode the comp a re v a l u e do ub le bu ffer i s only u pd a ted when the timer eq ua l s min ( u nder- flow). thi s g ua r a ntee s th a t the re su lting w a veform i s a lw a y s s ymmetric a l a ro u nd the top v a l u e as s hown in fig u re 13-10 b ec aus e the u p a nd down co u nt comp a re v a l u e s a re identic a l. the tf2 interr u pt fl a g i s only s et a t u nderflow. 13.4.2.2 phase correct pwm when t2cm 1-0 = 11b the s ymmetric a l pwm oper a te s in ph as e correct mode. in thi s mode the comp a re v a l u e do ub le bu ffer i s u pd a ted when the timer eq ua l s min ( u nderflow) a nd top (over- flow). the re su lting w a veform m a y not b e completely s ymmetric a l a ro u nd the top v a l u e as s hown in fig u re 13-11 b ec aus e the u p a nd down co u nt comp a re v a l u e s m a y not b e identic a l. however, thi s a llow s the p u l s e s to b e weighted tow a rd one edge or a nother. the tf2 interr u pt fl a g i s s et a t b oth u nderflow a nd overflow. f out o s cill a tor freq u ency 2 rcap2h rcap2l {,} ----------------------------------------------------------------- 1 tp s 1 + -------------------- - = non-inverting: d u ty cycle 100% ccxh ccxl {,} rcap2h rcap2l {,} ------------------------------------------------------ = inverting: d u ty cycle 100% rcap2h rcap2l {,} ccxh ccxl {,} ? rcap2h rcap2l {,} -------------------------------------------------------------------------------------------------- - = {rcap2h,rca2l} cp/rl2 = 0, t2cm 1-0 = 10b, dcen = 0 (inverted) cca {ccah,ccal} (non-inverted) ccb {ccbh,ccbl}
80 3706c?micro?2/11 at89lp3240/6440 figure 13-10. ph as e a nd freq u ency correct s ymmetric a l (center-aligned) pwm figure 13-11. ph as e correct s ymmetric a l (center-aligned) pwm 13.4.3 multi-phasic pwm the pwm ch a nnel s m a y b e config u red to provide m u lti-ph as ic a ltern a ting o u tp u t s b y the ph s 2-0 b it s in t2mod. the at 8 9lp3240/6440 provide s 1 o u t of 2, 1 o u t of 3, 1 o u t of 4 a nd 2 o u t of 4 ph as e mode s ( s ee t ab le 13-6 ). in m u lti-ph as ic mode the pwm o u tp u t s on cca, ccb, ccc a nd ccd a re connected to a one-hot s hift regi s ter th a t s electively en ab le s a nd di sab le s the o u tp u t s ( s ee fig u re 13-12 ). comp a re point s on di sab led ch a nnel s a re b locked from toggling the o u tp u t as if the comp a re v a l u e w as s et eq ua l to top. the ph s d b it in t2mod control s the direction of the s hift regi s ter. ex a mple w a veform s a re s hown in fig u re 13-14 on p a ge 8 2 . in order to us e m u lti-ph as ic pwm, the ass oci a ted ch a nnel s m us t b e config u red for pwm oper a tion. non-pwm ch a nnel s a re not a ffected b y m u lti-ph as ic oper a tion. however, their loc a tion s in the s hift regi s ter a re m a int a ined su ch th a t s ome period s in the pwm o u tp u t s m a y not h a ve a ny p u l s e s as s hown in fig u re 13-13 . the ph s 2-0 b it s m a y only b e modified when the timer i s not oper a tion a l (tr2 = 0). upd a te s to ph s d a re a llowed a t a ny time. note th a t ch a nnel s c a nd d in 1:2 ph as e mode a nd ch a nnel d in 1:3 ph as e mode oper a te norm a lly. {rcap2h,rca2l} cp/rl2 = 0, t2cm 1-0 = 10b, dcen = 0 inverted {ccxh,ccxl} non-inverted ccx d u ty cycle upd a ted {rcap2h,rca2l} cp/rl2 = 0, t2cm 1-0 = 11b, dcen = 0 inverted {ccxh,ccxl} non-inverted ccx d u ty cycle upd a ted
81 3706c?micro?2/11 at89lp3240/6440 figure 13-12. m u lti-ph as ic pwm o u tp u t s t a ge figure 13-13. three-ph as e mode with ch a nnel b di sab led table 13-6. su mm a ry of m u lti-ph as ic mode s phs 2-0 mode behavior phsd = 0 phsd = 1 000 off norm a l oper a tion ( a ll ch a nnel s a ctive a t a ll time s ) 001 1:2 010 1:3 011 1:4 100 2:4 abab cdcd dcdc s d ph s d ph s = 001b cca en 1 ccb en 0 ccc en 0 ccd en 1 ph s d ph s d ph s = 010b cca en 1 ccb en 0 ccc en 0 ccd en 0 ph s d ph s d ph s = 011b cca en 1 ccb en 0 ccc en 1 ccd en 0 ph s d ph s d ph s = 100b ph s d ph s d cca ccb ccc ph s d ph s = 010b, ccb di sab led
82 3706c?micro?2/11 at89lp3240/6440 figure 13-14. m u lti-ph as ic pwm mode s 14. external interrupts the int0 (p3.2) a nd int1 (p3.3) pin s of the at 8 9lp3240/6440 m a y b e us ed as extern a l inter- r u pt s o u rce s . the extern a l interr u pt s c a n b e progr a mmed to b e level- a ctiv a ted or tr a n s ition- a ctiv a ted b y s etting or cle a ring b it it1 or it0 in regi s ter tcon. if itx = 0, extern a l interr u pt x i s triggered b y a detected low a t the intx pin. if itx = 1, extern a l interr u pt x i s edge-triggered. in thi s mode if su cce ss ive sa mple s of the intx pin s how a high in one cycle a nd a low in the next cycle, interr u pt req u e s t fl a g iex in tcon i s s et. fl a g b it iex then req u e s t s the interr u pt. s ince the extern a l interr u pt pin s a re sa mpled once e a ch clock cycle, a n inp u t high or low s ho u ld hold for a t le as t 2 o s cill a tor period s to en su re sa mpling. if the extern a l interr u pt i s tr a n s ition- a ctiv a ted, the extern a l s o u rce h as to hold the req u e s t pin high for a t le as t two clock cycle s , a nd then hold it low for a t le as t two clock cycle s to en su re th a t the tr a n s ition i s s een s o th a t interr u pt req u e s t fl a g iex will b e s et. iex will b e au tom a tic a lly cle a red b y the cpu when the s ervice ro u tine i s c a lled if gen- er a ted in edge-triggered mode. if the extern a l interr u pt i s level- a ctiv a ted, the extern a l s o u rce h as to hold the req u e s t a ctive u ntil the req u e s ted interr u pt i s a ct ua lly gener a ted. then the extern a l s o u rce m us t de a ctiv a te the req u e s t b efore the interr u pt s ervice ro u tine i s completed, or el s e cca ccb ccc ccd cca ccb ccc ccd cca ccb ccc ccd ph s d cca ccb ccc ccd ph s d cca ccb ccc ccd ph s = 000b ph s = 001b ph s = 010b ph s = 011b ph s = 100b
83 3706c?micro?2/11 at89lp3240/6440 a nother interr u pt will b e gener a ted. both int0 a nd int1 m a y w a ke u p the device from the power-down s t a te. 15. general-purpose interrupts the gener a l-p u rpo s e interr u pt (gpi) f u nction provide s 8 config u r ab le extern a l interr u pt s on port 1. e a ch port pin c a n detect high/low level s or po s itive/neg a tive edge s . the gpien regi s ter s elect which b it s of port 1 a re en ab led to gener a te a n interr u pt. the gpmod a nd gpl s regi s - ter s determine the mode for e a ch individ ua l pin. gpmod s elect s b etween level- s en s itive a nd edge-triggered mode. gpl s s elect s b etween high/low in level mode a nd po s itive/neg a tive in edge mode. a b lock di a gr a m i s s hown in fig u re 15-1 . the pin s of port 1 a re sa mpled every clock cycle. in level- s en s itive mode, a v a lid level m us t a ppe a r in two su cce ss ive sa mple s b efore gener a ting the interr u pt. in edge-triggered mode, a tr a n s ition will b e detected if the v a l u e ch a nge s from one sa mple to the next. when a n interr u pt condition on a pin i s detected, a nd th a t pin i s en ab led, the a ppropri a te fl a g in the gpif regi s ter i s s et. the fl a g s in gpif m us t b e cle a red b y s oftw a re. any gpi interr u pt m a y w a ke u p the device from the power-down s t a te. figure 15-1. gpi block di a gr a m dq 2 2 2 2 00 1 1 (p1.2) gpi2 dq 1 1 1 1 00 1 1 (p1.1) gpi1 dq 0 0 0 0 00 1 1 (p1.0) gpi0 dq 3 3 3 3 00 1 1 (p1. 3 ) gpi 3 dq 6 6 6 6 00 1 1 (p1.6) gpi6 dq 5 5 5 5 00 1 1 (p1.5) gpi5 dq 4 4 4 4 00 1 1 (p1.4) gpi4 dq 7 7 7 7 00 1 1 (p1.7) gpi7 gpmod gpls gpien gpif interrupt clk
84 3706c?micro?2/11 at89lp3240/6440 . . . table 15-1. gpmod ? gener a l-p u rpo s e interr u pt mode regi s ter gpmod = 9ah re s et v a l u e = 0000 0000b not bit addre ssab le gpmod7 gpmod6 gpmod5 gpmod4 gpmod3 gpmod2 gpmod1 gpmod0 bit76543210 gpmod.x 0 = level- s en s itive interr u pt for p1.x 1 = edge-triggered interr u pt for p1.x table 15-2. gpl s ? gener a l-p u rpo s e interr u pt level s elect regi s ter gpl s = 9bh re s et v a l u e = 0000 0000b not bit addre ssab le gpl s 7gpl s 6gpl s 5gpl s 4gpl s 3gpl s 2gpl s 1gpl s 0 bit76543210 gpmod.x 0 = detect low level or neg a tive edge on p1.x 1 = detect high level or po s itive edge on p1.x table 15-3. gpien ? gener a l-p u rpo s e interr u pt en ab le regi s ter gpien = 9ch re s et v a l u e = 0000 0000b not bit addre ssab le gpien7 gpien6 gpien5 gpien4 gpien3 gpien2 gpien1 gpien0 bit76543210 gpien.x 0 = interr u pt for p1.x di sab led 1 = interr u pt for p1.x en ab led table 15-4. gpif ? gener a l-p u rpo s e interr u pt fl a g regi s ter gpif = 9dh re s et v a l u e = 0000 0000b not bit addre ssab le gpif7 gpif6 gpif5 gpif4 gpif3 gpif2 gpif1 gpif0 bit76543210 gpif.x 0 = interr u pt on p1.x in a ctive 1 = interr u pt on p1.x a ctive. m us t b e cle a red b y s oftw a re.
85 3706c?micro?2/11 at89lp3240/6440 16. serial interface (uart) the s eri a l interf a ce on the at 8 9lp3240/6440 implement s a univer sa l a s ynchrono us receiver/tr a n s mitter (uart). the uart h as the following fe a t u re s : ?f u ll-d u plex oper a tion ? 8 or 9 d a t a bit s ?fr a ming error detection ?m u ltiproce ss or comm u nic a tion mode with a u tom a tic addre ss recognition ?b au d r a te gener a tor u s ing timer 1 or timer 2 ? interr u pt on receive b u ffer f u ll or tr a n s mi ss ion complete the s eri a l interf a ce i s f u ll-d u plex, which me a n s it c a n tr a n s mit a nd receive s im u lt a neo us ly. it i s a l s o receive- bu ffered, which me a n s it c a n b egin receiving a s econd b yte b efore a previo us ly received b yte h as b een re a d from the receive regi s ter. (however, if the fir s t b yte s till h as not b een re a d when reception of the s econd b yte i s complete, one of the b yte s will b e lo s t.) the s eri a l port receive a nd tr a n s mit regi s ter s a re b oth a cce ss ed a t the s peci a l f u nction regi s ter s buf. writing to s buf lo a d s the tr a n s mit regi s ter, a nd re a ding s buf a cce ss e s a phy s ic a lly s ep a r a te receive regi s ter. the s eri a l port c a n oper a te in the following fo u r mode s . ? mode 0: s eri a l d a t a enter s a nd exit s thro u gh rxd. txd o u tp u t s the s hift clock. eight d a t a b it s a re tr a n s mitted/received, with the l s b fir s t. the bau d r a te i s progr a mm ab le to 1/2 or 1/4 the o s cill a tor freq u ency, or v a ri ab le bas ed on time 1. ? mode 1: 10 b it s a re tr a n s mitted (thro u gh txd) or received (thro u gh rxd): a s t a rt b it (0), 8 d a t a b it s (l s b fir s t), a nd a s top b it (1). on receive, the s top b it goe s into rb 8 in the s peci a l f u nction regi s ter s con. the bau d r a te i s v a ri ab le bas ed on timer 1 or timer 2. ? mode 2: 11 b it s a re tr a n s mitted (thro u gh txd) or received (thro u gh rxd): a s t a rt b it (0), 8 d a t a b it s (l s b fir s t), a progr a mm ab le 9th d a t a b it, a nd a s top b it (1). on tr a n s mit, the 9th d a t a b it (tb 8 in s con) c a n b e ass igned the v a l u e of ?0? or ?1?. for ex a mple, the p a rity b it (p, in the p s w) c a n b e moved into tb 8 . on receive, the 9th d a t a b it goe s into rb 8 in the s peci a l f u nction regi s ter s con, while the s top b it i s ignored. the bau d r a te i s progr a mm ab le to either 1/16 or 1/32 the o s cill a tor freq u ency. ? mode 3: 11 b it s a re tr a n s mitted (thro u gh txd) or received (thro u gh rxd): a s t a rt b it (0), 8 d a t a b it s (l s b fir s t), a progr a mm ab le 9th d a t a b it, a nd a s top b it (1). in f a ct, mode 3 i s the sa me as mode 2 in a ll re s pect s except the bau d r a te, which i s v a ri ab le bas ed on timer 1 or timer 3 in mode 3. in a ll fo u r mode s , tr a n s mi ss ion i s initi a ted b y a ny in s tr u ction th a t us e s s buf as a de s tin a tion regi s ter. reception i s initi a ted in mode 0 b y the condition ri = 0 a nd ren = 1. reception i s initi- a ted in the other mode s b y the incoming s t a rt b it if ren = 1. 16.1 multiprocessor communications mode s 2 a nd 3 h a ve a s peci a l provi s ion for m u ltiproce ss or comm u nic a tion s . in the s e mode s , 9d a t a b it s a re received, followed b y a s top b it. the 9th b it goe s into rb 8 . then come s a s top b it. the port c a n b e progr a mmed su ch th a t when the s top b it i s received, the s eri a l port interr u pt i s a ctiv a ted only if rb 8 = 1. thi s fe a t u re i s en ab led b y s etting b it s m2 in s con. the following ex a mple s how s how to us e the s eri a l interr u pt for m u ltiproce ss or comm u nic a tion s . when the m as ter proce ss or m us t tr a n s mit a b lock of d a t a to one of s ever a l s l a ve s , it fir s t s end s o u t a n a ddre ss b yte th a t identifie s the t a rget s l a ve. an a ddre ss b yte differ s from a d a t a b yte in th a t the 9th b it i s ?1? in a n a ddre ss b yte a nd ?0? in a d a t a b yte. with s m2 = 1, no s l a ve i s interr u pted b y a d a t a b yte. an a ddre ss b yte, however, interr u pt s a ll s l a ve s . e a ch s l a ve c a n ex a mine the received b yte a nd s ee if it i s b eing a ddre ss ed. the a ddre ss ed s l a ve cle a r s it s s m2
86 3706c?micro?2/11 at89lp3240/6440 b it a nd prep a re s to receive the d a t a b yte s th a t follow s . the s l a ve s th a t a re not a ddre ss ed s et their s m2 b it s a nd ignore the d a t a b yte s . s ee ?a u tom a tic addre ss recognition? on p a ge 97. the s m2 b it c a n b e us ed to check the v a lidity of the s top b it in mode 1. in a mode 1 reception, if s m2 = 1, the receive interr u pt i s not a ctiv a ted u nle ss a v a lid s top b it i s received. note s :1. s mod0 i s loc a ted a t pcon.6. 2. f o s c = o s cill a tor freq u ency. the bau d r a te depend s on s mod1 (pcon.7). table 16-1. s con ? s eri a l port control regi s ter s con addre ss = 9 8 h re s et v a l u e = 0000 0000b bit addre ssab le s m0/fe s m1 s m2 ren tb 8 rb 8 t1 ri bit7 6543210 ( s mod0 = 0/1) (1) symbol function fe fr a ming error b it. thi s b it i s s et b y the receiver when a n inv a lid s top b it i s detected. the fe b it i s not cle a red b y v a lid fr a me s a nd m us t b e cle a red b y s oftw a re. the s mod0 b it m us t b e s et to en ab le a cce ss to the fe b it. fe will b e s et reg a rdle ss of the s t a te of s mod0. s m0 s eri a l port mode bit 0, ( s mod0 m us t = 0 to a cce ss b it s m0) s m1 s eri a l port mode bit 1 s m2 en ab le s the a u tom a tic addre ss recognition fe a t u re in mode s 2 or 3. if s m2 = 1 then rl will not b e s et u nle ss the received 9th d a t a b it (rb 8 ) i s 1, indic a ting a n a ddre ss , a nd the received b yte i s a given or bro a dc as t addre ss . in mode 1, if s m2 = 1 then rl will not b e a ctiv a ted u nle ss a v a lid s top b it w as received, a nd the received b yte i s a given or bro a dc as t addre ss . in mode 0, s m2 determine s the idle s t a te of the s hift clock su ch th a t the clock i s the inver s e of s m2, i.e. when s m2 = 0 the clock idle s high a nd when s m2 = 1 the clock idle s low. ren en ab le s s eri a l reception. s et b y s oftw a re to en ab le reception. cle a r b y s oftw a re to di sab le reception. tb 8 the 9th d a t a b it th a t will b e tr a n s mitted in mode s 2 a nd 3. s et or cle a r b y s oftw a re as de s ired. in mode 0, s etting tb 8 en ab le s timer 1 as the s hift clock gener a tor. rb 8 in mode s 2 a nd 3, the 9th d a t a b it th a t w as received. in mode 1, if s m2 = 0, rb 8 i s the s top b it th a t w as received. in mode 0, rb 8 i s not us ed. ti tr a n s mit interr u pt fl a g. s et b y h a rdw a re a t the end of the 8 th b it time in mode 0, or a t the b eginning of the s top b it in the other mode s , in a ny s eri a l tr a n s mi ss ion. m us t b e cle a red b y s oftw a re. ri receive interr u pt fl a g. s et b y h a rdw a re a t the end of the 8 th b it time in mode 0, or h a lfw a y thro u gh the s top b it time in the other mode s , in a ny s eri a l reception (except s ee s m2). m us t b e cle a red b y s oftw a re. sm0 sm1 mode description baud rate (2) 000 s hift regi s ter f o s c /2 or f o s c /4 or timer 1 011 8 - b it uart v a ri ab le (timer 1 or timer 2) 1029- b it uart f o s c /32 or f o s c /16 1139- b it uart v a ri ab le (timer 1 or timer 2)
87 3706c?micro?2/11 at89lp3240/6440 16.2 baud rates the bau d r a te in mode 0 depend s on the v a l u e of the s mod1 b it in s peci a l f u nction regi s ter pcon.7. if s mod1 = 0 (the v a l u e on re s et) a nd tb 8 = 0, the bau d r a te i s 1/4 of the o s cill a tor freq u ency. if s mod1 = 1 a nd tb 8 =0, the bau d r a te i s 1/2 of the o s cill a tor freq u ency, as s hown in the following eq ua tion: the bau d r a te in mode 2 a l s o depend s on the v a l u e of the s mod1 b it. if s mod1 = 0, the bau d r a te i s 1/32 of the o s cill a tor freq u ency. if s mod1 = 1, the bau d r a te i s 1/16 of the o s cill a tor fre- q u ency, as s hown in the following eq ua tion: 16.2.1 using timer 1 to generate baud rates s etting tb 8 = 1 in mode 0 en ab le s timer 1 as the bau d r a te gener a tor. when timer 1 i s the bau d r a te gener a tor for mode 0, the bau d r a te s a re determined b y the timer 1 overflow r a te a nd the v a l u e of s mod1 a ccording to the following eq ua tion: the timer 1 overflow r a te norm a lly determine s the bau d r a te s in mode s 1 a nd 3. when timer 1 i s the bau d r a te gener a tor, the bau d r a te s a re determined b y the timer 1 overflow r a te a nd the v a l u e of s mod1 a ccording to the following eq ua tion: the timer 1 interr u pt s ho u ld b e di sab led in thi s a pplic a tion. the timer it s elf c a n b e config u red for either timer or co u nter oper a tion in a ny of it s 3 r u nning mode s . in the mo s t typic a l a pplic a - tion s , it i s config u red for timer oper a tion in au to-relo a d mode (high ni bb le of tmod = 0010b). in thi s c as e, the bau d r a te i s given b y the following form u l a : progr a mmer s c a n a chieve very low bau d r a te s with timer 1 b y config u ring the timer to r u n as a 16- b it au to-relo a d timer (high ni bb le of tmod = 0001b). in thi s c as e, the bau d r a te i s given b y the following form u l a . t ab le 16-2 li s t s commonly us ed bau d r a te s a nd how they c a n b e o b t a ined from timer 1. mode 0 b au d r a te tb 8 = 0 2 s mod1 4 -------------------- o s cill a tor freq u ency = mode 2 b au d r a te 2 s mod1 32 -------------------- o s cill a tor freq u ency = mode 0 b au d r a te tb 8 = 1 2 s mod1 4 -------------------- (timer 1 overflow r a te) = mode s 1, 3 b au d r a te 2 s mod1 32 -------------------- (timer 1 overflow r a te) = mode s 1, 3 b au d r a te 2 s mod1 32 -------------------- o s cill a tor freq u ency 256 th1 () ? [] ------------------------------------------------------ - 1 tp s 1 + -------------------- - = mode s 1, 3 b au d r a te 2 s mod1 32 -------------------- o s cill a tor freq u ency 65536 rh1,rl1 () ? [] -------------------------------------------------------- - 1 tp s 1 + -------------------- - =
88 3706c?micro?2/11 at89lp3240/6440 16.2.2 using timer 2 to generate baud rates timer 2 i s s elected as the bau d r a te gener a tor b y s etting tclk a nd/or rclk in t2con. under the s e condition s , the bau d r a te s for tr a n s mit a nd receive c a n b e s im u lt a neo us ly different b y us ing timer 1 for tr a n s mit a nd timer 2 for receive, or vice ver sa . the bau d r a te gener a tor mode i s s imil a r to the au to-relo a d mode, in th a t a rollover c aus e s the timer 2 regi s ter s to b e relo a ded with the 16- b it v a l u e in regi s ter s rcap2h a nd rcap2l, which a re pre s et b y s oftw a re. in thi s c as e, the bau d r a te s in mode s 1 a nd 3 a re determined b y timer 2? s overflow r a te a ccording to the following eq ua tion:. t ab le 16-3 li s t s commonly us ed bau d r a te s a nd how they c a n b e o b t a ined from timer 2. table 16-2. commonly u s ed b au d r a te s gener a ted b y timer 1 (tp s = 0000b) baud rate f osc (mhz) smod1 timer 1 c/t mode reload value mode 0: 1 mhz 4 0 x x x mode 2: 750k 12 1 x x x 62.5k 12 1 0 2 f4h 3 8 .4k 11.059 0 0 2 f7h 19.2k 11.059 1 0 2 dch 9.6k 11.059 0 0 2 dch 4. 8 k 11.059 0 0 2 b 8 h 2.4k 11.059 0 0 2 70h 1.2k 11.059 0 0 1 fee0h 137.5 11.9 8 6001f55ch 110 6 0 0 1 f95 8 h 110 12 0 0 1 f304h table 16-3. commonly u s ed b au d r a te s gener a ted b y timer 2 (tp s = 0000b) baud rate f osc (mhz) timer 2 cp/rl2 c/t2 tclk or rclk reload value 62.5k 12 0 0 1 fff4h 19.2k 11.059 0 0 1 ffdch 9.6k 11.059 0 0 1 ffb 8 h 4. 8 k 11.059 0 0 1 ff70h 2.4k 11.059 0 0 1 fee0h 1.2k 11.059 0 0 1 fdc0h 137.5 11.9 8 6 0 0 1 eab 8 h 110 6 0 0 1 f2afh 110 12 0 0 1 e55eh mode s 1 a nd 3 b au d r a te 1 16 ------ o s cill a tor freq u ency 65536 rcap2h,rcap2l () ? [] --------------------------------------------------------------------------------- 1 tp s 1 + -------------------- - =
89 3706c?micro?2/11 at89lp3240/6440 16.3 more about mode 0 in mode 0, the uart i s config u red as a two wire h a lf-d u plex s ynchrono us s eri a l interf a ce. s eri a l d a t a enter s a nd exit s thro u gh rxd. txd o u tp u t s the s hift clock. eight d a t a b it s a re tr a n s mit- ted/received, with the l s b fir s t. fig u re 16-1 on p a ge 90 s how s a s implified f u nction a l di a gr a m of the s eri a l port in mode 0 a nd ass oci a ted timing. the bau d r a te i s progr a mm ab le to 1/2 or 1/4 the o s cill a tor freq u ency b y s etting/cle a ring the s mod1 b it. however, ch a nging s mod1 h as a n effect on the rel a tion s hip b etween the clock a nd d a t a as de s cri b ed b elow. the bau d r a te c a n a l s o b e gener a ted b y timer 1 b y s etting tb 8 . t ab le 16-4 li s t s the bau d r a te option s for mode 0. tr a n s mi ss ion i s initi a ted b y a ny in s tr u ction th a t us e s s buf as a de s tin a tion regi s ter. the ?write to s buf? s ign a l a l s o lo a d s a ?1? into the 9th po s ition of the tr a n s mit s hift regi s ter a nd tell s the tx control block to b egin a tr a n s mi ss ion. the intern a l timing i s su ch th a t one f u ll b it s lot m a y el a p s e b etween ?write to s buf? a nd a ctiv a tion of s end. s end tr a n s fer s the o u tp u t of the s hift regi s ter to the a ltern a te o u tp u t f u nction line of p3.0, a nd a l s o tr a n s fer s s hift clock to the a ltern a te o u tp u t f u nction line of p3.1. a s d a t a b it s s hift o u t to the right, ?0? s come in from the left. when the m s b of the d a t a b yte i s a t the o u tp u t po s ition of the s hift regi s ter, the ?1? th a t w as initi a lly lo a ded into the 9th po s ition i s j us t to the left of the m s b, a nd a ll po s ition s to the left of th a t cont a in ?0? s . thi s condition fl a g s the tx control b lock to do one l as t s hift, then de a ctiv a te s end a nd s et ti. reception i s initi a ted b y the condition ren = 1 a nd r1 = 0. at the next clock cycle, the rx con- trol u nit write s the b it s 11111110 to the receive s hift regi s ter a nd a ctiv a te s receive in the next clock ph as e. receive en ab le s s hift clock to the a ltern a te o u tp u t f u nction line of p3.1. a s d a t a b it s come in from the right, ?1? s s hift o u t to the left. when the ?0? th a t w as initi a lly lo a ded into the right-mo s t po s ition a rrive s a t the left-mo s t po s ition in the s hift regi s ter, it fl a g s the rx control b lock to do one l as t s hift a nd lo a d s buf. then receive i s cle a red a nd ri i s s et. the rel a tion s hip b etween the s hift clock a nd d a t a i s determined b y the com b in a tion of the s m2 a nd s mod1 b it s as li s ted in t ab le 16-5 a nd s hown in fig u re 16-2 . the s m2 b it determine s the idle s t a te of the clock when not c u rrently tr a n s mitting/receiving. the s mod1 b it determine s if the o u tp u t d a t a i s s t ab le for b oth edge s of the clock, or j us t one. table 16-4. mode 0 b au d r a te s tb8 smod1 baud rate 00 f s y s /4 01 f s y s /2 1 0 (timer 1 overflow) / 4 1 1 (timer 1 overflow) / 2 table 16-5. mode 0 clock a nd d a t a mode s sm2 smod1 clock idle data changed data sampled 0 0 high while clock i s high po s itive edge of clock 0 1 high neg a tive edge of clock po s itive edge of clock 1 0 low while clock i s low neg a tive edge of clock 1 1 low neg a tive edge of clock po s itive edge of clock
90 3706c?micro?2/11 at89lp3240/6440 figure 16-1. s eri a l port mode 0 internal bu s f o s c internal bu s txd ( s hift clock) rxd (data out) txd ( s hift clock) rxd (data in) write to s buf s end s hift ti write to s con (clear ri) s hift receive ri ?1? 2 tb 8 0 1 timer 1 overflow 2 s mod1 0 1 s m2
91 3706c?micro?2/11 at89lp3240/6440 figure 16-2. mode 0 w a veform s mode 0 m a y b e us ed as a h a rdw a re a cceler a tor for s oftw a re em u l a tion of s eri a l interf a ce s su ch as a h a lf-d u plex s eri a l peripher a l interf a ce ( s pi) in mode (0,0) or (1,1) or a two-wire interf a ce (twi) in m as ter mode. an ex a mple of mode 0 em u l a ting a twi m as ter device i s s hown in fig u re 16-3 . in thi s ex a mple, the s t a rt, s top, a nd a cknowledge a re h a ndled in s oftw a re while the b yte tr a n s mi ss ion i s done in h a rdw a re. f a lling/ri s ing edge s on txd a re cre a ted b y s etting/cle a ring s m2. ri s ing/f a lling edge s on rxd a re forced b y s etting/cle a ring the p3.0 regi s ter b it. s m2 a nd p3.0 m us t b e 1 while the b yte i s b eing tr a n s ferred. figure 16-3. uart mode 0 twi em u l a tion ( s mod1 = 1) mode 0 tr a n s fer s d a t a l s b fir s t where as s pi or twi a re gener a lly m s b fir s t. em u l a tion of the s e interf a ce s m a y req u ire b it rever sa l of the tr a n s ferred d a t a b yte s . the following code ex a mple rever s e s the b it s in the a cc u m u l a tor: ex: mov r7, #8 revrs: rlc a ; c << msb(acc) xch a, r6 rrc a ; msb(acc) >> b xch a, r6 djnz r7, revrs 7 rxd (tx) txd 6 5 4 3 2 1 0 rxd (rx) 01234567 7 rxd (tx) txd 6 5 4 3 2 1 0 rxd (rx) 01234567 7 rxd (tx) txd 6 5 4 3 2 1 0 rxd (rx) 01234567 7 rxd (tx) txd 6 5 4 3 2 1 0 rxd (rx) 01234567 s mod1 = 0 s m2 = 0 s mod1 = 1 s m2 = 0 s mod1 = 0 s m2 = 1 s mod1 = 1 s m2 = 1 7 ( s da) rxd ( s cl) txd 6 5 4 3 2 1 0 ack s m2 p3.0 write to s buf ti sa mple ack
92 3706c?micro?2/11 at89lp3240/6440 16.4 more about mode 1 ten b it s a re tr a n s mitted (thro u gh txd), or received (thro u gh rxd): a s t a rt b it (0), 8 d a t a b it s (l s b fir s t), a nd a s top b it (1). on receive, the s top b it goe s into rb 8 in s con. in the at 8 9lp3240/6440, the bau d r a te i s determined either b y the timer 1 overflow r a te, the timer 2 overflow r a te, or b oth. in thi s c as e one timer i s for tr a n s mit a nd the other i s for receive. fig u re 16-4 s how s a s implified f u nction a l di a gr a m of the s eri a l port in mode 1 a nd ass oci a ted timing s for tr a n s mit a nd receive. tr a n s mi ss ion i s initi a ted b y a ny in s tr u ction th a t us e s s buf as a de s tin a tion regi s ter. the ?write to s buf? s ign a l a l s o lo a d s a ?1? into the 9th b it po s ition of the tr a n s mit s hift regi s ter a nd fl a g s the tx control u nit th a t a tr a n s mi ss ion i s req u e s ted. tr a n s mi ss ion a ct ua lly commence s a t s 1p1 of the m a chine cycle following the next rollover in the divide- b y-16 co u nter. th us , the b it time s a re s ynchronized to the divide- b y-16 co u nter, not to the ?write to s buf? s ign a l. the tr a n s mi ss ion b egin s when s end i s a ctiv a ted, which p u t s the s t a rt b it a t txd. one b it time l a ter, data i s a ctiv a ted, which en ab le s the o u tp u t b it of the tr a n s mit s hift regi s ter to txd. the fir s t s hift p u l s e occ u r s one b it time a fter th a t. a s d a t a b it s s hift o u t to the right, ?0? s a re clocked in from the left. when the m s b of the d a t a b yte i s a t the o u tp u t po s ition of the s hift regi s ter, the ?1? th a t w as initi a lly lo a ded into the 9th po s ition i s j us t to the left of the m s b, a nd a ll po s ition s to the left of th a t cont a in ?0? s . thi s condition fl a g s the tx control u nit to do one l as t s hift, then de a ctiv a te s end a nd s et ti. thi s occ u r s a t the tenth divide- b y-16 rollover a fter ?write to s buf.? reception i s initi a ted b y a 1-to-0 tr a n s ition detected a t rxd. for thi s p u rpo s e, rxd i s sa mpled a t a r a te of 16 time s the e s t ab li s hed bau d r a te. when a tr a n s ition i s detected, the divide- b y-16 co u nter i s immedi a tely re s et, a nd 1ffh i s written into the inp u t s hift regi s ter. re s etting the divide- b y-16 co u nter a lign s it s roll-over s with the b o u nd a rie s of the incoming b it time s . the 16 s t a te s of the co u nter divide e a ch b it time into 16th s . at the 7th, 8 th, a nd 9th co u nter s t a te s of e a ch b it time, the b it detector sa mple s the v a l u e of rxd. the v a l u e a ccepted i s the v a l u e th a t w as s een in a t le as t 2 of the 3 sa mple s . thi s i s done to reject noi s e. in order to reject f a l s e b it s , if the v a l u e a ccepted d u ring the fir s t b it time i s not 0, the receive circ u it s a re re s et a nd the u nit contin u e s looking for a nother 1-to-0 tr a n s ition. if the s t a rt b it i s v a lid, it i s s hifted into the inp u t s hift regi s ter, a nd reception of the re s t of the fr a me proceed s . a s d a t a b it s come in from the right, ?1? s s hift o u t to the left. when the s t a rt b it a rrive s a t the left- mo s t po s ition in the s hift regi s ter, (which i s a 9- b it regi s ter in mode 1), it fl a g s the rx control b lock to do one l as t s hift, lo a d s buf a nd rb 8 , a nd s et ri. the s ign a l to lo a d s buf a nd rb 8 a nd to s et ri i s gener a ted if, a nd only if, the fo llowing condition s a re met a t the time the fin a l s hift p u l s e i s gener a ted. ri = 0 a nd either s m2 = 0, or the received s top b it = 1 if either of the s e two condition s i s not met, the received fr a me i s irretriev ab ly lo s t. if b oth condi- tion s a re met, the s top b it goe s into rb 8 , the 8 d a t a b it s go into s buf, a nd ri i s a ctiv a ted. at thi s time, whether or not the ab ove condition s a re met, the u nit contin u e s looking for a 1-to-0 tr a n s ition in rxd.
93 3706c?micro?2/11 at89lp3240/6440 figure 16-4. s eri a l port mode 1 tx clock write to s buf internal bu s read s buf load s buf s buf s hift input s hift reg. (9 bit s ) bit detector 1-to-0 tran s ition detector s erial port interrupt write to s buf 2 s mod1 ?0? ?1? timer 1 overflow rxd rx clock rx clock rx control s tart s tart data s end s ample 16 16 tx control ti t i zero detector s buf txd internal bu s ?1? d q cl s load s buf s hift s hift 1ffh ri s end data s hift txd ti d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 s top bit tran s mit s tart bit 16 re s et s tart bit s top bit rx clock bit detector s ample time s s hift receive rxd ri timer 2 overflow tclk rclk ?0? ?0? ?1? ?1?
94 3706c?micro?2/11 at89lp3240/6440 16.5 more about modes 2 and 3 eleven b it s a re tr a n s mitted (thro u gh txd), or received (thro u gh rxd): a s t a rt b it (0), 8 d a t a b it s (l s b fir s t), a progr a mm ab le 9th d a t a b it, a nd a s top b it (1). on tr a n s mit, the 9th d a t a b it (tb 8 ) c a n b e ass igned the v a l u e of ?0? or ?1?. on receive, the 9th d a t a b it goe s into rb 8 in s con. the bau d r a te i s progr a mm ab le to either 1/16 or 1/32 of the o s cill a tor freq u ency in mode 2. mode 3 m a y h a ve a v a ri ab le bau d r a te gener a ted from either timer 1 or timer 2, depending on the s t a te of rclk a nd tclk. fig u re s 16-5 a nd 16-6 s how a f u nction a l di a gr a m of the s eri a l port in mode s 2 a nd 3. the receive portion i s ex a ctly the sa me as in mode 1. the tr a n s mit portion differ s from mode 1 only in the 9th b it of the tr a n s mit s hift regi s ter. tr a n s mi ss ion i s initi a ted b y a ny in s tr u ction th a t us e s s buf as a de s tin a tion regi s ter. the ?write to s buf? s ign a l a l s o lo a d s tb 8 into the 9th b it po s ition of the tr a n s mit s hift regi s ter a nd fl a g s the tx control u nit th a t a tr a n s mi ss ion i s req u e s ted. tr a n s mi ss ion commence s a t s 1p1 of the m a chine cycle following the next rollover in the divide- b y-16 co u nter. th us , the b it time s a re s yn- chronized to the divide- b y-16 co u nter, not to the ?write to s buf? s ign a l. the tr a n s mi ss ion b egin s when s end i s a ctiv a ted, which p u t s the s t a rt b it a t txd. one b it time l a ter, data i s a ctiv a ted, which en ab le s the o u tp u t b it of the tr a n s mit s hift regi s ter to txd. the fir s t s hift p u l s e occ u r s one b it time a fter th a t. the fir s t s hift clock s a ?1? (the s top b it) into the 9th b it po s ition of the s hift regi s ter. there a fter, only ?0? s a re clocked in. th us , as d a t a b it s s hift o u t to the right, ?0? s a re clocked in from the left. when tb 8 i s a t the o u tp u t po s ition of the s hift regi s ter, then the s top b it i s j us t to the left of tb 8 , a nd a ll po s ition s to the left of th a t cont a in ?0? s . thi s con- dition fl a g s the tx control u nit to do one l as t s hift, then de a ctiv a te s end a nd s et ti. thi s occ u r s a t the 11th divide- b y-16 rollover a fter ?write to s buf.? reception i s initi a ted b y a 1-to-0 tr a n s ition detected a t rxd. for thi s p u rpo s e, rxd i s sa mpled a t a r a te of 16 time s the e s t ab li s hed bau d r a te. when a tr a n s ition i s detected, the divide- b y-16 co u nter i s immedi a tely re s et, a nd 1ffh i s written to the inp u t s hift regi s ter. at the 7th, 8 th a nd 9th co u nter s t a te s of e a ch b it time, the b it detector sa mple s the v a l u e of rxd. the v a l u e a ccepted i s the v a l u e th a t w as s een in a t le as t 2 of the 3 sa mple s . if the v a l u e a ccepted d u ring the fir s t b it time i s not 0, the receive circ u it s a re re s et a nd the u nit contin u e s looking for a nother 1-to-0 tr a n s ition. if the s t a rt b it prove s v a lid, it i s s hifted into the inp u t s hift regi s ter, a nd reception of the re s t of the fr a me proceed s . a s d a t a b it s come in from the right, ?1? s s hift o u t to the left. when the s t a rt b it a rrive s a t the left- mo s t po s ition in the s hift regi s ter (which in mode s 2 a nd 3 i s a 9- b it regi s ter), it fl a g s the rx con- trol b lock to do one l as t s hift, lo a d s buf a nd rb 8 , a nd s et ri. the s ign a l to lo a d s buf a nd rb 8 a nd to s et ri i s gener a ted if, a nd only if, the fo llowing condition s a re met a t the time the fin a l s hift p u l s e i s gener a ted: ri = 0, a nd either s m2 = 0 or the received 9th d a t a b it = 1 if either of the s e condition s i s not met, the received fr a me i s irretriev ab ly lo s t, a nd ri i s not s et. if b oth condition s a re met, the received 9th d a t a b it goe s into rb 8 , a nd the fir s t 8 d a t a b it s go into s buf. one b it time l a ter, whether the ab ove condition s were met or not, the u nit contin u e s look- ing for a 1-to-0 tr a n s ition a t the rxd inp u t. note th a t the v a l u e of the received s top b it i s irrelev a nt to s buf, rb 8 , or ri.
95 3706c?micro?2/11 at89lp3240/6440 figure 16-5. s eri a l port mode 2 s mod1 1 s mod1 0 internal bu s internal bu s cpu clock
96 3706c?micro?2/11 at89lp3240/6440 figure 16-6. s eri a l port mode 3 tx clock write to s buf s end data s hift txd s top bit gen ti d0 d1 d2 d3 d4 d5 d6 d7 tb 8 s top bit tran s mit s tart bit internal bu s read s buf load s buf s buf s hift input s hift reg. (9 bit s ) bit detector 1-to-0 tran s ition detector s erial port interrupt write to s buf 2 s mod1 timer 1 overflow rxd rx clock rx clock rx control s ta rt s ta rt data s ample 16 16 tx control ti zero detector s buf txd internal bu s tb 8 d q cl s load s buf s hift 1ffh s hift ri s end d0 d1 d2 d3 d4 d5 d6 d7 rb 8 s tart bit s top bit 16 re s et rx clock bit detector s ample time s s hift receive rxd ri s top bit timer 2 overflow tclk rclk ?0? ?0? ?1? ?1? ?0? ?1?
97 3706c?micro?2/11 at89lp3240/6440 16.6 framing error detection in a ddition to a ll of it s usua l mode s , the uart c a n perform fr a ming error detection b y looking for mi ss ing s top b it s , a nd au tom a tic a ddre ss recognition. when us ed for fr a ming error detect, the uart look s for mi ss ing s top b it s in the comm u nic a tion. a mi ss ing b it will s et the fe b it in the s con regi s ter. the fe b it s h a re s the s con.7 b it with s m0 a nd the f u nction of s con.7 i s deter- mined b y pcon.6 ( s mod0). if s mod0 i s s et then s con.7 f u nction s as fe. s con.7 f u nction s as s m0 when s mod0 i s cle a red. when us ed as fe, s con.7 c a n only b e cle a red b y s oftw a re. the fe b it will b e s et b y a fr a ming error reg a rdle ss of the s t a te of s mod0. 16.7 automatic ad dress recognition a u tom a tic addre ss recognition i s a fe a t u re which a llow s the uart to recognize cert a in a ddre ss e s in the s eri a l b it s tre a m b y us ing h a rdw a re to m a ke the comp a ri s on s . thi s fe a t u re sa ve s a gre a t de a l of s oftw a re overhe a d b y elimin a ting the need for the s oftw a re to ex a mine every s eri a l a ddre ss which p ass e s b y the s eri a l port. thi s fe a t u re i s en ab led b y s etting the s m2 b it in s con for mode s 1, 2 or 3. in the 9- b it uart mode s , mode 2 a nd mode 3, the receive interr u pt fl a g (ri) will b e au tom a tic a lly s et when the received b yte cont a in s either the ?given? a ddre ss or the ?bro a dc as t? a ddre ss . the 9- b it mode req u ire s th a t the 9th inform a tion b it b e a ?1? to indic a te th a t the received inform a tion i s a n a ddre ss a nd not d a t a . in mode 1 ( 8 - b it) the ri fl a g will b e s et if s m2 i s en ab led a nd the inform a tion received h as a v a lid s top b it following the 8 th a ddre ss b it s a nd the inform a tion i s either a given or bro a dc as t a ddre ss . a u tom a tic addre ss recognition i s not a v a il ab le d u ring mode 0. u s ing the a u tom a tic addre ss recognition fe a t u re a llow s a m as ter to s electively comm u nic a te with one or more s l a ve s b y invoking the given s l a ve a ddre ss or a ddre ss e s . all of the s l a ve s m a y b e cont a cted b y us ing the bro a dc as t a ddre ss . two s peci a l f u nction regi s ter s a re us ed to define the s l a ve? s a ddre ss , s addr, a nd the a ddre ss m as k, s aden. s aden i s us ed to define which b it s in the s addr a re to b e us ed a nd which b it s a re ?don?t c a re?. the s aden m as k c a n b e logic a lly anded with the s addr to cre a te the ?given? a ddre ss which the m as ter will us e for a ddre ss ing e a ch of the s l a ve s . u s e of the given a ddre ss a llow s m u ltiple s l a ve s to b e recognized while excl u ding other s . the following ex a mple s s how the ver sa tility of thi s s cheme: s l a ve 0 s addr = 1100 0000 s aden = 1111 1101 given = 1100 00x0 s l a ve 1 s addr = 1100 0000 s aden = 1111 1110 given = 1100 000x in the previo us ex a mple, s addr i s the sa me a nd the s aden d a t a i s us ed to differenti a te b etween the two s l a ve s . s l a ve 0 req u ire s a ?0? in b it 0 a nd it ignore s b it 1. s l a ve 1 req u ire s a ?0? in b it 1 a nd b it 0 i s ignored. a u niq u e a ddre ss for s l a ve 0 wo u ld b e 1100 0010 s ince s l a ve 1 req u ire s a ?0? in b it 1. a u niq u e a ddre ss for s l a ve 1 wo u ld b e 1100 0001 s ince a ?1? in b it 0 will excl u de s l a ve 0. both s l a ve s c a n b e s elected a t the sa me time b y a n a ddre ss which h as b it 0 = 0 (for s l a ve 0) a nd b it 1 = 0 (for s l a ve 1). th us , b oth co u ld b e a ddre ss ed with 1100 0000.
98 3706c?micro?2/11 at89lp3240/6440 in a more complex s y s tem, the following co u ld b e us ed to s elect s l a ve s 1 a nd 2 while excl u ding s l a ve 0: s l a ve 0 s addr = 1100 0000 s aden = 1111 1001 given = 1100 0xx0 s l a ve 1 s addr = 1110 0000 s aden = 1111 1010 given = 1110 0x0x s l a ve 2 s addr = 1110 0000 s aden = 1111 1100 given = 1110 00xx in the ab ove ex a mple, the differenti a tion a mong the 3 s l a ve s i s in the lower 3 a ddre ss b it s . s l a ve 0 req u ire s th a t b it 0 = 0 a nd it c a n b e u niq u ely a ddre ss ed b y 1110 0110. s l a ve 1 req u ire s th a t b it 1 = 0 a nd it c a n b e u niq u ely a ddre ss ed b y 1110 a nd 0101. s l a ve 2 req u ire s th a t b it 2 = 0 a nd it s u niq u e a ddre ss i s 1110 0011. to s elect s l a ve s 0 a nd 1 a nd excl u de s l a ve 2, us e a ddre ss 1110 0100, s ince it i s nece ssa ry to m a ke b it 2 = 1 to excl u de s l a ve 2. the bro a dc as t addre ss for e a ch s l a ve i s cre a ted b y t a king the logic or of s addr a nd s aden. zero s in thi s re su lt a re trended as don?t c a re s . in mo s t c as e s , interpreting the don?t c a re s as one s , the b ro a dc as t a ddre ss will b e ff hex a decim a l. upon re s et s addr ( s fr a ddre ss 0a9h) a nd s aden ( s fr a ddre ss 0b9h) a re lo a ded with ?0? s . thi s prod u ce s a given a ddre ss of a ll ?don?t c a re s ? as well as a bro a dc as t a ddre ss of a ll ?don?t c a re s ?. thi s effectively di sab le s the a u tom a tic addre ss ing mode a nd a llow s the microcon- troller to us e s t a nd a rd 8 0c51-type uart driver s which do not m a ke us e of thi s fe a t u re. 17. enhanced serial peripheral interface the s eri a l peripher a l interf a ce ( s pi) a llow s high- s peed s ynchrono us d a t a tr a n s fer b etween the at 8 9lp3240/6440 a nd peripher a l device s or b etween m u ltiple at 8 9lp3240/6440 device s , incl u ding m u ltiple m as ter s a nd s l a ve s on a s ingle bus . the s pi incl u de s the following fe a t u re s : ?f u ll-d u plex, 3-wire or 4-wire s ynchrono us d a t a tr a n s fer ?m as ter or s l a ve oper a tion ?m a xim u m bit freq u ency = f o s c /4 ?l s b fir s t or m s b fir s t d a t a tr a n s fer ?fo u r progr a mm ab le bit r a te s or timer 1- bas ed b au d gener a tion (m as ter mode) ?end of tr a n s mi ss ion interr u pt fl a g ? write colli s ion fl a g protection ?do ub le- bu ffered receive a nd tr a n s mit ?tr a n s mit b u ffer empty interr u pt fl a g ? mode f au lt (m as ter colli s ion) detection a nd interr u pt ?w a ke u p from idle mode a b lock di a gr a m of the s pi i s s hown b elow in fig u re 17-1 .
99 3706c?micro?2/11 at89lp3240/6440 figure 17-1. s pi block di a gr a m the interconnection b etween m as ter a nd s l a ve cpu s with s pi i s s hown in fig u re 17-2 . the fo u r pin s in the interf a ce a re m as ter-in/ s l a ve-o u t (mi s o), m as ter-o u t/ s l a ve-in (mo s i), s hift clock ( s ck), a nd s l a ve s elect ( ss ). the s ck pin i s the clock o u tp u t in m as ter mode, bu t i s the clock inp u t in s l a ve mode. the m s tr b it in s pcr determine s the direction s of mi s o a nd mo s i. al s o notice th a t mo s i connect s to mo s i a nd mi s o to mi s o. by def au lt ss /p1.4 i s a n inp u t to b oth m as ter a nd s l a ve device s . in s l a ve mode, ss m us t b e driven low to s elect a n individ ua l device as a s l a ve. when ss i s held low, the s pi i s a ctiv a ted, a nd mi s o b ecome s a n o u tp u t if config u red s o b y the us er. all other pin s a re inp u t s . when ss i s driven high, a ll pin s a re inp u t s , a nd the s pi i s p ass ive, which me a n s th a t it will not receive incoming d a t a . note th a t the s pi logic will b e re s et once the ss pin i s driven high. the ss pin i s us ef u l for p a cket/ b yte s ynchroniz a tion to keep the s l a ve b it co u nter s ynchrono us with the m as ter clock gener a tor. when the ss pin i s driven high, the s pi s l a ve will immedi a tely re s et the s end a nd receive logic, a nd drop a ny p a rti a lly received d a t a in the s hift regi s ter.the s l a ve m a y ignore ss b y s etting it s ss ig b it in s p s r. when ss ig = 1, the s l a ve i s a lw a y s en ab led a nd oper a te s in 3-wire mode. however, the s l a ve o u tp u t on mi s o m a y s till b e di sab led b y s etting di ss o=1. the in- s y s tem progr a mming (i s p) interf a ce a l s o us e s the s pi pin s . altho u gh the i s p protocol i s s pi- bas ed, the ss pin h as s peci a l me a ning a nd m us t b e driven b y the m as ter as a fr a me delim- iter. ss c a nnot b e tied to gro u nd for i s p to f u nction correctly. oscillator 8-bit shift register read data buffer pin control logic spi control spi status register spi interrupt re q uest internal data bus select spi clock (master) divider 4/8/ 3 2/64 spi control register 8 8 8 spif wcol spr1 mstr tsck clock logic msb s m spe dord mstr cpol cpha spr1 spr0 mstr spe dord lsb s m m s miso p1.6 mosi p1.5 sck 1.7 ss p1.4 spr0 spe write data buffer modf txe enh tsck 0 1 t1 ovf disso ssig
100 3706c?micro?2/11 at89lp3240/6440 figure 17-2. s pi m as ter- s l a ve interconnection when the s pi i s config u red as a m as ter (m s tr in s pcr i s s et), the oper a tion of the ss pin depend s on the s etting of the s l a ve s elect ignore b it, ss ig. if ss ig = 1, the ss pin i s a gener a l p u rpo s e o u tp u t pin which doe s not a ffect the s pi s y s tem. typic a lly, the pin will b e driving the ss pin of a n s pi s l a ve. if ss ig = 0, ss m us t b e held high to en su re m as ter s pi oper a tion. if the ss pin i s driven low b y peripher a l circ u itry when the s pi i s config u red as a m as ter with ss ig = 0, the s pi s y s tem interpret s thi s as a nother m as ter s electing the s pi as a s l a ve a nd s t a rting to s end d a t a to it. to a void bus contention, the s pi s y s tem t a ke s the following a ction s : 1. the m s tr b it in s pcr i s cle a red a nd the s pi s y s tem b ecome s a s l a ve. a s a re su lt of the s pi b ecoming a s l a ve, the mo s i a nd s ck pin s b ecome inp u t s . 2. the modf fl a g in s p s r i s s et, a nd if the s pi interr u pt i s en ab led, the interr u pt ro u tine will b e exec u ted. th us , when interr u pt-driven s pi tr a n s mi ss ion i s us ed in m as ter mode, a nd there exi s t s a po ss i- b ility th a t ss m a y b e driven low, the interr u pt s ho u ld a lw a y s check th a t the m s tr b it i s s till s et. if the m s tr b it h as b een cle a red b y a s l a ve s elect, it m us t b e s et b y the us er to re-en ab le s pi m as ter mode. 17.1 master operation an s pi m as ter device initi a te s a ll d a t a tr a n s fer s on the s pi bus . the at 8 9lp3240/6440 i s con- fig u red for m as ter oper a tion b y s etting m s tr = 1 in s pcr. writing to the s pi d a t a regi s ter ( s pdr) while in m as ter mode lo a d s the tr a n s mit bu ffer. if the s pi s hift regi s ter i s empty, the b yte in the tr a n s mit bu ffer i s moved to the s hift regi s ter; the tr a n s mit bu ffer empty fl a g, txe, i s s et; a nd a tr a n s mi ss ion b egin s . the tr a n s fer m a y s t a rt a fter a n initi a l del a y, while the clock gener a tor w a it s for the next f u ll b it s lot of the s pecified bau d r a te. the m as ter s hift s the d a t a o u t s eri a lly on the mo s i line while providing the s eri a l s hift clock on s ck. when the tr a n s fer fini s he s , the s pif fl a g i s s et to ?1? a nd a n interr u pt req u e s t i s gener a ted, if en ab led. the d a t a received from the a ddre ss ed s pi s l a ve device i s a l s o tr a n s ferred from the s hift regi s ter to the receive bu ffer. therefore, the s pif b it fl a g s b oth the tr a n s mit-complete a nd receive-d a t a -re a dy condition s . the received d a t a i s a cce ss ed b y re a ding s pdr. while the txe fl a g i s s et, the tr a n s mit bu ffer i s empty. txe c a n b e cle a red b y s oftw a re or b y writing to s pdr. writing to s pdr will cle a r txe a nd lo a d the tr a n s mit bu ffer. the us er m a y lo a d the bu ffer while the s hift regi s ter i s bus y, i.e. b efore the c u rrent tr a n s fer complete s . when the c u rrent tr a n s fer complete s , the q u e u ed b yte in the tr a n s mit bu ffer i s moved to the s hift regi s ter a nd the next tr a n s fer commence s . txe will gener a te a n interr u pt if the s pi interr u pt i s en ab led 8-bit shift register master slave msb lsb msb lsb 8-bit shift register miso miso disso ssig mosi mosi ss ss gpio ssig v cc sck sck modf clock generator
101 3706c?micro?2/11 at89lp3240/6440 a nd if the enh b it in s p s r i s s et. for m u lti- b yte tr a n s fer s , txe m a y b e us ed to remove a ny de a d time b etween b yte tr a n s mi ss ion s . the s pi m as ter c a n oper a te in two mode s : m u lti-m as ter mode a nd s ingle-m as ter mode. by def au lt, m u lti-m as ter mode i s a ctive when ss ig = 0. in thi s mode, the ss inp u t i s us ed to di s - ab le a m as ter device when a nother m as ter i s a cce ss ing the bus . when ss i s driven low, the m as ter device b ecome s a s l a ve b y cle a ring it s m s tr b it a nd a mode f au lt i s gener a ted b y s et- ting the modf b it in s p s r. modf will gener a te a n interr u pt if en ab led. the m s tr b it m us t b e s et in s oftw a re b efore the device m a y b ecome a m as ter a g a in. s ingle-m as ter mode i s en ab led b y s etting ss ig = 1. in thi s mode ss i s ignored a nd the m as ter i s a lw a y s a ctive. ss m a y b e us ed as a gener a l p u rpo s e i/o in thi s mode. 17.2 slave operation when the at 8 9lp3240/6440 i s not config u red for m as ter oper a tion, m s tr = 0, it will oper a te as a n s pi s l a ve. in s l a ve mode, b yte s a re s hifted in thro u gh mo s i a nd o u t thro u gh mi s o b y a m as - ter device controlling the s eri a l clock on s ck. when a b yte h as b een tr a n s ferred, the s pif fl a g i s s et to ?1? a nd a n interr u pt req u e s t i s gener a ted, if en ab led. the d a t a received from the a ddre ss ed m as ter device i s a l s o tr a n s ferred from the s hift regi s ter to the receive bu ffer. the received d a t a i s a cce ss ed b y re a ding s pdr. a s l a ve device c a nnot initi a te tr a n s fer s . d a t a to b e tr a n s ferred to the m as ter device m us t b e prelo a ded b y writing to s pdr. write s to s pdr a re do ub le- bu ffered. the tr a n s mit bu ffer i s lo a ded fir s t a nd if the s hift regi s ter i s empty, the content s of the bu ffer will b e tr a n s ferred to the s hift regi s ter. while the txe fl a g i s s et, the tr a n s mit bu ffer i s empty. txe c a n b e cle a red b y s oftw a re or b y writing to s pdr. writing to s pdr will cle a r txe a nd lo a d the tr a n s mit bu ffer. the us er m a y lo a d the bu ffer while the s hift regi s ter i s bus y, i.e. b efore the c u rrent tr a n s fer complete s . when the c u rrent tr a n s fer complete s , the q u e u ed b yte in the tr a n s mit bu ffer i s moved to the s hift regi s ter a nd w a it s for the m as ter to initi a te a nother tr a n s fer. txe will gener a te a n interr u pt if the s pi interr u pt i s en ab led a nd if the enh b it in s p s r i s s et. the s pi s l a ve c a n oper a te in two mode s : 4-wire mode a nd 3-wire mode. by def au lt, 4-wire mode i s a ctive when ss ig = 0. in thi s mode, the ss inp u t i s us ed to en ab le/di sab le the s l a ve device when a ddre ss ed b y a m as ter. when ss i s driven low, the s l a ve device i s en ab led a nd will s hift o u t d a t a on mi s o in re s pon s e to the s eri a l clock on s ck. while ss i s high, the s pi s l a ve will rem a in s leeping with mi s o in a ctive. three-wire mode i s en ab led b y s etting ss ig = 1. in thi s mode ss i s ignored a nd the s l a ve i s a lw a y s a ctive. ss m a y b e us ed as a gener a l p u rpo s e i/o in thi s mode. the di sab le s l a ve o u tp u t b it, di ss o in s p s r, m a y b e us ed to di sab le the mi s o line of a s l a ve device. di ss o c a n a llow s ever a l s l a ve device s to s h a re mi s o while oper a ting in 3-wire mode. in thi s c as e s ome protocol other th a n ss m a y b e us ed to determine which s l a ve i s en ab led. 17.3 pin configuration when the s pi i s en ab led ( s pe = 1), the d a t a direction of the mo s i, mi s o, s ck, a nd ss pin s i s au tom a tic a lly overridden a ccording to the m s tr b it as s hown in t ab le 17-1 . the us er need not reconfig u re the pin s when s witching from m as ter to s l a ve or vice-ver sa . for more det a il s on port config u r a tion, refer to ?port config u r a tion? on p a ge 45 .
102 3706c?micro?2/11 at89lp3240/6440 . note s :1.in the s e mode s mo s i i s a ctive only d u ring tr a n s fer s . mo s i will b e p u lled high b etween tr a n s - fer s to a llow other m as ter s to control the line. 2. in p us h-p u ll mode mo s i i s a ctive only d u ring tr a n s fer s , otherwi s e it i s tri s t a ted to prevent line contention. a we a k extern a l p u ll- u p m a y b e req u ired to prevent mo s i from flo a ting. table 17-1. s pi pin config u r a tion a nd beh a vior when s pe = 1 pin mode master (mstr = 1) slave (mstr = 0) s ck q uas i- b idirection a lo u tp u tinp u t (intern a l p u ll- u p) p us h-p u ll o u tp u to u tp u tinp u t (tri s t a te) inp u t-only no o u tp u t (tri s t a ted) inp u t (tri s t a te) open-dr a in o u tp u to u tp u t inp u t (extern a l p u ll- u p) mo s i q uas i- b idirection a lo u tp u t (1) inp u t (intern a l p u ll- u p) p us h-p u ll o u tp u to u tp u t (2) inp u t (tri s t a te) inp u t-only no o u tp u t (tri s t a ted) inp u t (tri s t a te) open-dr a in o u tp u to u tp u t (1) inp u t (extern a l p u ll- u p) mi s o q uas i- b idirection a linp u t (intern a l p u ll- u p) o u tp u t ( ss = 0) intern a l p u ll- u p ( ss = 1 or di ss o = 1) p us h-p u ll o u tp u tinp u t (tri s t a te) o u tp u t ( ss = 0) tr i s t a ted ( ss = 1 or di ss o = 1) inp u t-only inp u t (tri s t a te) no o u tp u t (tri s t a ted) open-dr a in o u tp u tinp u t (extern a l p u ll- u p) o u tp u t ( ss = 0) extern a l p u ll- u p ( ss = 1 or di ss o = 1) table 17-2. s pcr ? s pi control regi s ter s pcr addre ss = e9h re s et v a l u e = 0000 0000b not bit addre ssab le t s ck s pe dord m s tr cpol cpha s pr1 s pr0 bit76543210 symbol function t s ck s ck clock mode. when t s ck = 0, the s ck bau d r a te i s bas ed on the s y s tem clock, divided b y the s pr 1-0 r a tio.when t s ck = 1, the s ck bau d r a te i s bas ed on the timer 1 overflow r a te, divided b y the s pr 1-0 r a tio. s pe s pi en ab le. s pi = 1 en ab le s the s pi ch a nnel a nd connect s ss , mo s i, mi s o a nd s ck to pin s p1.4, p1.5, p1.6, a nd p1.7. s pi = 0 di sab le s the s pi ch a nnel. dord d a t a order. dord = 1 s elect s l s b fir s t d a t a tr a n s mi ss ion. dord = 0 s elect s m s b fir s t d a t a tr a n s mi ss ion. m s tr m as ter/ s l a ve s elect. m s tr = 1 s elect s m as ter s pi mode. m s tr = 0 s elect s s l a ve s pi mode. cpol clock pol a rity. when cpol = 1, s ck i s high when idle. when cpol = 0, s ck of the m as ter device i s low when not tr a n s mitting. ple as e refer to fig u re on s pi clock ph as e a nd pol a rity control. cpha clock ph as e. the cpha b it together with the cpol b it control s the clock a nd d a t a rel a tion s hip b etween m as ter a nd s l a ve. ple as e refer to fig u re on s pi clock ph as e a nd pol a rity control.
103 3706c?micro?2/11 at89lp3240/6440 note s :1. s et u p the clock mode b efore en ab ling the s pi: s et a ll b it s needed in s pcr except the s pe b it, then s et s pe. 2. en ab le the m as ter s pi prior to the s l a ve device. 3. s l a ve echoe s m as ter on the next tx if not lo a ded with new d a t a . s pr0 s pr1 s pi clock r a te s elect. the s e two b it s control the s ck r a te of the device config u red as m as ter. s pr1 a nd s pr0 h a ve no effect on the s l a ve. the rel a tion s hip b etween s ck a nd the o s cill a tor freq u ency, f o s c. , i s as follow s : s pr1 s pr0 s ck (t s ck = 0) s ck (t s ck = 1) 00f o s c /4 f t1ovf /4 01f o s c / 8 f t1ovf / 8 10f o s c /32 f t1ovf /32 11f o s c /64 f t1ovf /64 symbol function table 17-3. s pdr ? s pi d a t a regi s ter s pdr addre ss = eah re s et v a l u e= 00h ( a fter cold re s et) u nch a nged ( a fter w a rm re s et) not bit addre ssab le s pd7 s pd6 s pd5 s pd4 s pd3 s pd2 s pd1 s pd0 bit76543210 table 17-4. s p s r ? s pi s t a t us regi s ter s p s r addre ss = e 8 h re s et v a l u e = 0000 x000b not bit addre ssab le s pif wcol modf txe ? ss ig di ss oenh bit76543210 symbol function s pif s pi tr a n s fer complete interr u pt fl a g. when a s eri a l tr a n s fer i s complete, the s pif b it i s s et b y h a rdw a re a nd a n interr u pt i s gener a ted if e s p = 1. the s pif b it m a y b e cle a red b y s oftw a re or b y re a ding the s pi s t a t us regi s ter followed b y re a ding/writing the s pi d a t a regi s ter. wcol write colli s ion fl a g. the wcol b it i s s et b y h a rdw a re if s pdr i s written while the tr a n s mit bu ffer i s f u ll. the ongoing tr a n s fer i s not a ffected. wcol m a y b e cle a red b y s oftw a re or b y re a ding the s pi s t a t us regi s ter followed b y re a ding/writing the s pi d a t a regi s ter. modf mode f au lt fl a g. modf i s s et b y h a rdw a re when a m as ter mode colli s ion i s detected (m s tr = 1, ss ig = 0 a nd ss = 0) a nd a n interr u pt i s gener a ted if e s p= 1. modf m us t b e cle a red b y s oftw a re. txe tr a n s mit b u ffer empty fl a g. s et b y h a rdw a re when the tr a n s mit bu ffer i s lo a ded into the s hift regi s ter, a llowing a new b yte to b e lo a ded. txe m us t b e cle a red b y s oftw a re. when enh = 1 a nd e s p = 1, txe will gener a te a n interr u pt.
104 3706c?micro?2/11 at89lp3240/6440 17.4 serial clock timing the cpha, cpol a nd s pr b it s in s pcr control the s h a pe a nd r a te of s ck. the two s pr b it s provide fo u r po ss i b le clock r a te s when the s pi i s in m as ter mode. in s l a ve mode, the s pi will oper a te a t the r a te of the incoming s ck as long as it doe s not exceed the m a xim u m b it r a te. there a re a l s o fo u r po ss i b le com b in a tion s of s ck ph as e a nd pol a rity with re s pect to the s eri a l d a t a . cpha a nd cpol determine which form a t i s us ed for tr a n s mi ss ion. the s pi d a t a tr a n s fer form a t s a re s hown in fig u re s 17-3 a nd 17-4 . to prevent glitche s on s ck from di s r u pting the interf a ce, cpha, cpol, a nd s pr s ho u ld not b e modified while the interf a ce i s en ab led, a nd the m as ter device s ho u ld b e en ab led b efore the s l a ve device( s ). figure 17-3. s pi tr a n s fer form a t with cpha = 0 note: *not defined bu t norm a lly m s b of ch a r a cter j us t received. figure 17-4. s pi tr a n s fer form a t with cpha = 1 note: *not defined bu t norm a lly l s b of previo us ly tr a n s mitted ch a r a cter. ss ig s l a ve s elect ignore. if ss ig = 0, the s pi will only oper a te in s l a ve mode if ss (p1.4) i s p u lled low. when ss ig = 1, the s pi ignore s ss in s l a ve mode a nd i s a ctive whenever s pe ( s pcr.6) i s s et. when m s tr = 1 a nd ss ig = 0, ss i s monitored for m as ter mode colli s ion s . s etting ss ig = 1 will ignore colli s ion s on ss . p1.4 m a y b e us ed as a reg u l a r i/o pin when ss ig = 1. di ss o di sab le s l a ve o u tp u t b it. when s et, thi s b it c aus e s the mi s o pin to b e tri s t a ted s o th a t more th a n one s l a ve device c a n s h a re the sa me interf a ce witho u t m u ltiple ss line s . norm a lly, the fir s t b yte in a tr a n s mi ss ion co u ld b e the s l a ve a ddre ss a nd only the s elected s l a ve s ho u ld cle a r it s di ss o b it. enh tx b u ffer interr u pt en ab le. when enh = 1, txe will gener a te a n s pi interr u pt if e s p = 1. when enh = 0, txe doe s not gener a te a n interr u pt. msb 6 5 4 3 2 1 lsb 1 2 3 4 5 6 7 8 msb * 65432 1 lsb sck cycle # (for reference) sck (cpol = 0) sck (cpol = 1) mosi (from master) miso (from slave) ss (to slave)
105 3706c?micro?2/11 at89lp3240/6440 18. two-wire serial interface the two-wire interf a ce (twi) i s a b i-direction a l 2-wire s eri a l comm u nic a tion s t a nd a rd. it i s de s igned prim a rily for s imple bu t efficient integr a ted circ u it (ic) control. the s y s tem i s compri s ed of two line s , s cl ( s eri a l clock) a nd s da ( s eri a l d a t a ) th a t c a rry inform a tion b etween the ic s connected to them. the only extern a l h a rdw a re needed to implement the bus i s a s ingle p u ll- u p re s i s tor for e a ch of the twi bus line s . all device s connected to the bus h a ve individ ua l a ddre ss e s , a nd mech a ni s m s for re s olving bus contention a re inherent in the twi protocol. the s eri a l d a t a tr a n s fer i s limited to 400k b it/ s in s t a nd a rd mode. v a rio us comm u nic a tion config u r a - tion s c a n b e de s igned us ing thi s bus . fig u re 1 8 -1 s how s a typic a l 2-wire bus config u r a tion. any of the device s connected to the bus c a n b e m as ter or s l a ve. the two-wire interf a ce on the at 8 9lp provide s the following fe a t u re s : ? s imple yet powerf u l a nd flexi b le comm u nic a tion interf a ce, only two b us line s needed ? both m as ter a nd s l a ve oper a tion su pported ?device c a n oper a te as tr a n s mitter or receiver ?7- b it addre ss s p a ce allow s u p to 12 8 different s l a ve addre ss e s ?m u lti-m as ter ar b itr a tion su pport ? up to 400 khz d a t a tr a n s fer s peed ?f u lly progr a mm ab le s l a ve addre ss with gener a l c a ll su pport figure 18-1. two-wire b us config u r a tion a s depicted in fig u re 1 8 -1 , b oth bus line s a re connected to the po s itive su pply volt a ge thro u gh p u ll- u p re s i s tor s . the bus driver s of a ll twi-compli a nt device s a re open-dr a in or open-collector. thi s implement s a wired-and f u nction which i s e ss enti a l to the oper a tion of the interf a ce. a low level on a twi bus line i s gener a ted when one or more twi device s o u tp u t a zero. a high level i s o u tp u t when a ll twi device s tri s t a te their o u tp u t s , a llowing the p u ll- u p re s i s tor s to p u ll the line high. note th a t a ll at 8 9lp device s connected to the twi bus m us t b e powered in order to a llow a ny bus oper a tion. the n u m b er of device s th a t c a n b e connected to the bus i s only limited b y the bus c a p a cit a nce limit of 400 pf a nd the 7- b it s l a ve a ddre ss s p a ce. device 1 device 2 device 3 device n s da s cl ........ r1 r2 v cc
106 3706c?micro?2/11 at89lp3240/6440 18.1 data transfer and frame format 18.1.1 transferring bits e a ch d a t a b it tr a n s ferred on the twi bus i s a ccomp a nied b y a p u l s e on the clock line. the level of the d a t a line m us t b e s t ab le when the clock line i s high. the only exception to thi s r u le i s for gener a ting s t a rt a nd s top condition s . figure 18-2. d a t a v a lidity 18.1.2 start and stop conditions the m as ter initi a te s a nd termin a te s a d a t a tr a n s mi ss ion. the tr a n s mi ss ion i s initi a ted when the m as ter i ssu e s a s tart condition on the bus , a nd it i s termin a ted when the m as ter i ssu e s a s top condition. between a s tart a nd a s top condition, the bus i s con s idered bus y, a nd no other m as ter s ho u ld try to s eize control of the bus . a s peci a l c as e occ u r s when a new s tart condition i s i ssu ed b etween a s tart a nd s top condition. thi s i s referred to as a repeated s tart condition, a nd i s us ed when the m as ter wi s he s to initi a te a new tr a n s fer witho u t relin- q u i s hing control of the bus . after a repeated s tart, the bus i s con s idered bus y u ntil the next s top. thi s i s identic a l to the s tart b eh a vior, a nd therefore s tart i s us ed to de s cri b e b oth s tart a nd repeated s tart for the rem a inder of thi s d a t a s heet, u nle ss otherwi s e noted. a s depicted b elow, s tart a nd s top condition s a re s ign a lled b y ch a nging the level of the s da line when the s cl line i s high. figure 18-3. s tart, repeated s tart, a nd s top condition s 18.1.3 address packet format all a ddre ss p a cket s tr a n s mitted on the twi bus a re nine b it s long, con s i s ting of s even a ddre ss b it s , one read/write control b it a nd a n a cknowledge b it. if the read/write b it i s s et, a re a d oper a tion i s to b e performed, otherwi s e a write oper a tion s ho u ld b e performed. when a s l a ve recognize s th a t it i s b eing a ddre ss ed, it s ho u ld a cknowledge b y p u lling s da low in the ninth s cl (ack) cycle. if the a ddre ss ed s l a ve i s bus y, or for s ome other re as on c a n not s ervice the m as - sda scl data stable data stable data change sda scl start stop repeated start stop start
107 3706c?micro?2/11 at89lp3240/6440 ter? s req u e s t, the s da line s ho u ld b e left high in the ack clock cycle. the m as ter c a n then tr a n s mit a s top condition, or a repeated s tart condition to initi a te a new tr a n s mi ss ion. an a ddre ss p a cket con s i s ting of a s l a ve a ddre ss a nd a read or a write b it i s c a lled s la+r or s la+w, re s pectively. the m s b of the a ddre ss b yte i s tr a n s mitted fir s t. s l a ve a ddre ss e s c a n freely b e a lloc a ted b y the de s igner, bu t the a ddre ss 0000 000 i s re s erved for a gener a l c a ll. when a gener a l c a ll i s i ssu ed, a ll s l a ve s s ho u ld re s pond b y p u lling the s da line low in the ack cycle. a gener a l c a ll i s us ed when a m as ter wi s he s to tr a n s mit the sa me me ssa ge to s ever a l s l a ve s in the s y s tem. when the gener a l c a ll a ddre ss followed b y a write b it i s tr a n s mitted on the bus , a ll s l a ve s s et u p to a cknowledge the gener a l c a ll will p u ll the s da line low in the ack cycle. the following d a t a p a cket s will then b e received b y a ll the s l a ve s th a t a cknowledged the gener a l c a ll. note th a t tr a n s mitting the gener a l c a ll a ddre ss followed b y a re a d b it i s me a ningle ss , as thi s wo u ld c aus e contention if s ever a l s l a ve s s t a rted tr a n s mitting different d a t a . all a ddre ss e s of the form a t 1111 xxx s ho u ld b e re s erved for f u t u re p u rpo s e s . figure 18-4. addre ss p a cket form a t 18.1.4 data packet format all d a t a p a cket s tr a n s mitted on the twi bus a re nine b it s long, con s i s ting of one d a t a b yte a nd a n a cknowledge b it. d u ring a d a t a tr a n s fer, the m as ter gener a te s the clock a nd the s tart a nd s top condition s , while the receiver i s re s pon s i b le for a cknowledging the reception. an acknowledge (ack) i s s ign a lled b y the receiver p u lling the s da line low d u ring the ninth s cl cycle. if the receiver le a ve s the s da line high, a nack i s s ign a lled. when the receiver h as received the l as t b yte, or for s ome re as on c a nnot receive a ny more b yte s , it s ho u ld inform the tr a n s mitter b y s ending a nack a fter the fin a l b yte. the m s b of the d a t a b yte i s tr a n s mitted fir s t. figure 18-5. d a t a p a cket form a t sda scl start 12 789 addr msb addr lsb r/w ack 12 789 data msb data lsb ack aggregate sda sda from transmitter sda from receiver scl from master sla+r/w data byte stop, repeated start, or next data byte
108 3706c?micro?2/11 at89lp3240/6440 18.1.5 combining address and data packets into a transmission a tr a n s mi ss ion bas ic a lly con s i s t s of a s tart condition, a s la+r/w, one or more d a t a p a cket s a nd a s top condition. an empty me ssa ge, con s i s ting of a s tart followed b y a s top condi- tion, i s illeg a l. note th a t the wired-anding of the s cl line c a n b e us ed to implement h a nd s h a king b etween the m as ter a nd the s l a ve. the s l a ve c a n extend the s cl low period b y p u lling the s cl line low. thi s i s us ef u l if the clock s peed s et u p b y the m as ter i s too f as t for the s l a ve, or the s l a ve need s extr a time for proce ss ing b etween the d a t a tr a n s mi ss ion s . the s l a ve extending the s cl low period will not a ffect the s cl high period, which i s determined b y the m as ter. a s a con s eq u ence, the s l a ve c a n red u ce the twi d a t a tr a n s fer s peed b y prolonging the s cl d u ty cycle. fig u re 1 8 -6 s how s a typic a l d a t a tr a n s mi ss ion. note th a t s ever a l d a t a b yte s c a n b e tr a n s mitted b etween the s la+r/w a nd the s top condition, depending on the s oftw a re protocol imple- mented b y the a pplic a tion s oftw a re. figure 18-6. typic a l d a t a tr a n s mi ss ion 18.2 multi-master bus systems, arbitration and synchronization the twi protocol a llow s bus s y s tem s with s ever a l m as ter s . s peci a l concern s h a ve b een t a ken in order to en su re th a t tr a n s mi ss ion s will proceed as norm a l, even if two or more m as ter s initi a te a tr a n s mi ss ion a t the sa me time. two pro b lem s a ri s e in m u lti-m as ter s y s tem s : ?an a lgorithm m us t b e implemented a llowing only one of the m as ter s to complete the tr a n s mi ss ion. all other m as ter s s ho u ld ce as e tr a n s mi ss ion when they di s cover th a t they h a ve lo s t the s election proce ss . thi s s election proce ss i s c a lled a r b itr a tion. when a contending m as ter di s cover s th a t it h as lo s t the a r b itr a tion proce ss , it s ho u ld immedi a tely s witch to s l a ve mode to check whether it i s b eing a ddre ss ed b y the winning m as ter. the f a ct th a t m u ltiple m as ter s h a ve s t a rted tr a n s mi ss ion a t the sa me time s ho u ld not b e detect ab le to the s l a ve s (i.e., the d a t a b eing tr a n s ferred on the bus m us t not b e corr u pted). ? different m as ter s m a y us e different s cl freq u encie s . a s cheme m us t b e devi s ed to s ynchronize the s eri a l clock s from a ll m as ter s , in order to let the tr a n s mi ss ion proceed in a lock s tep f as hion. thi s will f a cilit a te the a r b itr a tion proce ss . the wired-anding of the bus line s i s us ed to s olve b oth the s e pro b lem s . the s eri a l clock s from a ll m as ter s will b e wired-anded, yielding a com b ined clock with a high period eq ua l to the one from the m as ter with the s horte s t high period. the low period of the com b ined clock i s eq ua l to the low period of the m as ter with the longe s t low period. note th a t a ll m as ter s li s ten to the s cl line, effectively s t a rting to co u nt their s cl high a nd low time-o u t period s when the com b ined s cl line goe s high or low, re s pectively. 12 789 data byte data msb data lsb ack sda scl start 12 789 addr msb addr lsb r/w ack sla+r/w stop
109 3706c?micro?2/11 at89lp3240/6440 figure 18-7. s cl s ynchroniz a tion b etween m u ltiple m as ter s ar b itr a tion i s c a rried o u t b y a ll m as ter s contin u o us ly monitoring the s da line a fter o u tp u tting d a t a . if the v a l u e re a d from the s da line doe s not m a tch the v a l u e the m as ter h a d o u tp u t, it h as lo s t the a r b itr a tion. note th a t a m as ter c a n only lo s e a r b itr a tion when it o u tp u t s a high s da v a l u e while a nother m as ter o u tp u t s a low v a l u e. the lo s ing m as ter s ho u ld immedi a tely go to s l a ve mode, checking if it i s b eing a ddre ss ed b y the winning m as ter. the s da line s ho u ld b e left high, bu t lo s ing m as ter s a re a llowed to gener a te a clock s ign a l u ntil the end of the c u rrent d a t a or a ddre ss p a cket. ar b itr a tion will contin u e u ntil only one m as ter rem a in s , a nd thi s m a y t a ke m a ny b it s . if s ever a l m as ter s a re trying to a ddre ss the sa me s l a ve, a r b itr a tion will contin u e into the d a t a p a cket. figure 18-8. ar b itr a tion b etween two m as ter s note th a t a r b itr a tion i s not a llowed b etween: ? a repeated s tart condition a nd a d a t a b it. ?a s top condition a nd a d a t a b it. ? a repeated s ta rt a nd a s top condition. ta low ta high scl from master a scl from master b scl bus line tb low tb high masters start counting low period masters start counting high period sda from master a sda from m sda line synchronized scl line start master a loses arbitration, sda a sda
110 3706c?micro?2/11 at89lp3240/6440 it i s the us er s oftw a re? s re s pon s i b ility to en su re th a t the s e illeg a l a r b itr a tion condition s never occ u r. thi s implie s th a t in m u lti-m as ter s y s tem s , a ll d a t a tr a n s fer s m us t us e the sa me compo s i- tion of s la+r/w a nd d a t a p a cket s . in other word s : all tr a n s mi ss ion s m us t cont a in the sa me n u m b er of d a t a p a cket s , otherwi s e the re su lt of the a r b itr a tion i s u ndefined. 18.3 overview of the twi module the twi mod u le i s compri s ed of s ever a l sub mod u le s , as s hown in fig u re 1 8 -9 . all regi s ter s dr a wn in a thick line a re a cce ss i b le thro u gh the at 8 9lp d a t a bus . figure 18-9. overview of the twi mod u le 18.3.1 scl and sda pins the s e pin s interf a ce the at 8 9lp twi with the re s t of the mcu s y s tem. the o u tp u t driver s con- t a in a s lew-r a te limiter in order to conform to the twi s pecific a tion. the inp u t s t a ge s cont a in a s pike su ppre ss ion u nit removing s pike s s horter th a n 50 n s . 18.3.2 bit rate generator unit thi s u nit control s the period of s cl when oper a ting in a m as ter mode. the s cl period i s con- trolled b y s etting s in the twi bit r a te regi s ter (twbr). s l a ve oper a tion doe s not depend on the bit r a te s etting, bu t the cpu clock freq u ency in the s l a ve m us t b e a t le as t 16 time s higher th a n the s cl freq u ency. note th a t s l a ve s m a y prolong the s cl low period, there b y red u cing the twi unit address register (twar) address match unit address comparator control unit control register (twcr) status register (twsr) state machine and status control scl slew-rate control spike filter sda slew-rate control spike filter bit rate generator bit rate register (twbr) prescaler bus interface unit start / stop control arbitration detection ack spike suppression address/data shift register (twdr)
111 3706c?micro?2/11 at89lp3240/6440 a ver a ge twi bus clock period. the s cl freq u ency i s gener a ted a ccording to the following eq ua tion: 18.3.3 bus interface unit thi s u nit cont a in s the d a t a a nd addre ss s hift regi s ter (twdr), a s tart/ s top controller a nd ar b itr a tion detection h a rdw a re. the twdr cont a in s the a ddre ss or d a t a b yte s to b e tr a n s mitted, or the a ddre ss or d a t a b yte s received. in a ddition to the 8 - b it twdr, the b us interf a ce unit a l s o cont a in s a regi s ter cont a ining the (n)ack b it to b e tr a n s mitted or received. thi s (n)ack regi s - ter i s not directly a cce ss i b le b y the a pplic a tion s oftw a re. however, when receiving, it c a n b e s et or cle a red b y m a nip u l a ting the twi control regi s ter (twcr). when in tr a n s mitter mode, the v a l u e of the received (n)ack b it c a n b e determined b y the v a l u e in the tw s r. the s tart/ s top controller i s re s pon s i b le for gener a tion a nd detection of s tart, repeated s tart, a nd s top condition s . if the twi h as initi a ted a tr a n s mi ss ion as m as ter, the ar b itr a tion detection h a rdw a re contin u - o us ly monitor s the tr a n s mi ss ion trying to determine if a r b itr a tion i s in proce ss . if the twi h as lo s t a n a r b itr a tion, the control unit i s informed. correct a ction c a n then b e t a ken a nd a ppropri a te s t a t us code s gener a ted. 18.3.4 address match unit the addre ss m a tch u nit check s if received a ddre ss b yte s m a tch the 7- b it a ddre ss in the twi addre ss regi s ter (twar). if the twi gener a l c a ll recognition en ab le (gc) b it in the twar i s written to one, a ll incoming a ddre ss b it s will a l s o b e comp a red a g a in s t the gener a l c a ll a ddre ss . upon a n a ddre ss m a tch, the control u nit i s informed, a llowing correct a ction to b e t a ken. the twi m a y or m a y not a cknowledge it s a ddre ss , depending on s etting s in the twcr. 18.3.5 control unit the control u nit monitor s the twi bus a nd gener a te s re s pon s e s corre s ponding to s etting s in the twi control regi s ter (twcr). when a n event req u iring the a ttention of the a pplic a tion occ u r s on the twi bus , the twi interr u pt fl a g (twif) i s ass erted. in the next clock cycle, the twi s t a - t us regi s ter (tw s r) i s u pd a ted with a s t a t us code identifying the event. the tw s r only cont a in s relev a nt s t a t us inform a tion when the twi interr u pt fl a g i s ass erted. at a ll other time s , the tw s r cont a in s a s peci a l s t a t us code indic a ting th a t no relev a nt s t a t us inform a tion i s a v a il- ab le. a s long as the twif fl a g i s s et, the s cl line i s held low. thi s a llow s the a pplic a tion s oftw a re to complete it s t as k s b efore a llowing the twi tr a n s mi ss ion to contin u e. the twif fl a g i s s et in the following s it ua tion s : ? after the twi h as tr a n s mitted a s tart/repeated s tart condition. ? after the twi h as tr a n s mitted s la+r/w. ? after the twi h as tr a n s mitted a n a ddre ss b yte. ? after the twi h as lo s t a r b itr a tion. ? after the twi h as b een a ddre ss ed b y own s l a ve a ddre ss or gener a l c a ll. ? after the twi h as received a d a t a b yte. ?after a s top or repeated s ta rt h as b een received while s till a ddre ss ed as a s l a ve. ? when a bus error h as occ u rred d u e to a n illeg a l s ta rt o r s top condition. s cl freq u ency s y s tem clock 16 twbr 1 + () --------------------------------------------- - =
112 3706c?micro?2/11 at89lp3240/6440 18.4 register overview table 18-1. twcr ? two-wire control regi s ter twcr addre ss = aah re s et v a l u e = x000 00xxb not bit addre ssab le ?twen s ta s to twif aa ? ? bit76543210 symbol function twen two-wire s eri a l interf a ce en ab le. s et to en ab le the twi. cle a r to di sab le the twi. s ta s t a rt fl a g. s et to s end a s tart condition on the bus . m us t b e cle a red b y s oftw a re. s to s top fl a g. s et to s end a s top condition on the bus . cle a red au tom a tic a lly b y h a rdw a re when the s top occ u r s . twif two-wire interf a ce interr u pt fl a g. s et b y h a rdw a re when the twi req u e s t s a n interr u pt. twif m us t b e cle a red b y s oftw a re. while twif i s s et, the s cl low period i s s tretched. note th a t cle a ring thi s fl a g s t a rt s the oper a tion of the twi, s o a ll a cce ss e s to the other twi regi s ter s (twar, tw s r a nd twdr) m us t b e complete b efore cle a ring thi s fl a g. aa a ss ert acknowledge fl a g. cle a r in m as ter a nd s l a ve receiver mode s , to force a not a cknowledge (high level on s da). cle a r to di sab le s la or gca recognition. s et to recognize s la or gca (if gc s et) for entering s l a ve receiver or tr a n s mitter mode s . s et in m as ter a nd s l a ve receiver mode s , to force a n a cknowledge (low level on s da). thi s b it h as no effect when in m as ter tr a n s mitter mode. by cle a ring aa to zero, the device c a n b e virt ua lly di s connected from the two- wire s eri a l b us tempor a rily. addre ss recognition c a n then b e re su med b y s etting the aa b it to one a g a in. table 18-2. tw s r ? two-wire s t a t us regi s ter tw s r addre ss = abh re s et v a l u e = 1111 1000b not bit addre ssab le tw s 7tw s 6tw s 5tw s 4tw s 3000 bit76543210 symbol function tw s 7-0 two-wire interf a ce s t a t us . the c u rrent s t a t us code of the twi logic a nd s eri a l bus . s ee t ab le 1 8 -6 thro u gh t ab le 1 8 -10 for a de s cription of the s t a t us code s . note th a t the three le as t s ignific a nt b it s a lw a y s re a d as zero. the s t a t us code i s v a lid only while twif rem a in s s et. table 18-3. twar ? two-wire addre ss regi s ter twar addre ss = ach re s et v a l u e = 1111 1110b not bit addre ssab le twa6 twa5 twa4 twa3 twa2 twa1 twa0 gc bit76543210 symbol function twa 6-0 two-wire interf a ce s l a ve addre ss . the twi will only re s pond to s l a ve a ddre ss e s th a t m a tch thi s 7- b it a ddre ss . gc gener a l c a ll en ab le. s et to en ab le gener a l c a ll a ddre ss (00h) recognition. cle a r to di sab le gener a l c a ll a ddre ss recognition.
113 3706c?micro?2/11 at89lp3240/6440 18.5 using the twi the at 8 9lp twi i s b yte-oriented a nd interr u pt bas ed. interr u pt s a re i ssu ed a fter a ll bus event s , like reception of a b yte or tr a n s mi ss ion of a s tart condition. bec aus e the twi i s interr u pt- bas ed, the a pplic a tion s oftw a re i s free to c a rry on other oper a tion s d u ring a twi b yte tr a n s fer. note th a t the twi interr u pt en ab le (twe) b it in ie2 together with the glo ba l interr u pt en ab le b it in ea a llow the a pplic a tion to decide whether or not ass ertion of the twif fl a g s ho u ld gener a te a n interr u pt req u e s t. if the twe b it i s cle a red, the a pplic a tion m us t poll the twif fl a g in order to detect a ction s on the twi bus . when the twif fl a g i s ass erted, the twi h as fini s hed a n oper a tion a nd a w a it s a pplic a tion re s pon s e. in thi s c as e, the twi s t a t us regi s ter (tw s r) cont a in s a v a l u e indic a ting the c u rrent s t a te of the twi bus . the a pplic a tion s oftw a re c a n then decide how the twi s ho u ld b eh a ve in the next twi bus cycle b y m a nip u l a ting the twcr a nd twdr regi s ter s . fig u re 1 8 -10 i s a s imple ex a mple of how the a pplic a tion c a n interf a ce to the twi h a rdw a re. in thi s ex a mple, a m as ter wi s he s to tr a n s mit a s ingle d a t a b yte to a s l a ve. thi s de s cription i s q u ite abs tr a ct, a more det a iled expl a n a tion follow s l a ter in thi s s ection. a s imple code ex a mple imple- menting the de s ired b eh a vior i s a l s o pre s ented. table 18-4. twdr ? two-wire d a t a regi s ter twdr addre ss = adh re s et v a l u e = 1111 1111b not bit addre ssab le twd7 twd6 twd5 twd4 twd3 twd2 twd1 twd0 bit76543210 symbol function twd 7-0 two-wire interf a ce d a t a . write s to twdr q u e u e the next a ddre ss or d a t a b yte for tr a n s mi ss ion. re a d s from twdr ret u rn the l as t a ddre ss or d a t a b yte pre s ent on the bus . write s /re a d s to/from twdr m us t occ u r only while twif i s s et. write s to twdr while twif = 0 a re ignored. re a d s from twdr while twif = 0 m a y ret u rn r a ndom d a t a . table 18-5. twbr ? two-wire bit r a te regi s ter twbr addre ss = aeh re s et v a l u e = 0000 0000b not bit addre ssab le twb7 twb6 twb5 twb4 twb3 twb2 twb1 twb0 bit76543210 symbol function twb 7-0 two-wire interf a ce s eri a l bit r a te. twbr i s a n 8 - b it down co u nter th a t s elect s the divi s ion f a ctor ( 1?256) for the b it r a te gener a tor. the b it r a te gener a tor i s a freq u ency divider which gener a te s the s cl clock freq u ency from the s y s tem clock in m as ter mode.
114 3706c?micro?2/11 at89lp3240/6440 figure 18-10. interf a cing the applic a tion to the twi in a typic a l tr a n s mi ss ion 1. the fir s t s tep in a twi tr a n s mi ss ion i s to tr a n s mit a s tart condition. thi s i s done b y writing a s pecific v a l u e into twcr, in s tr u cting the twi h a rdw a re to tr a n s mit a s ta rt condition. which v a l u e to write i s de s cri b ed l a ter on. however, it i s import a nt th a t the twif b it i s cle a red in the v a l u e written. the twi will not s t a rt a ny oper a tion as long as the twif b it in twcr i s s et. immedi a tely a fter the a pplic a tion h as cle a red twif, the twi will initi a te tr a n s mi ss ion of the s tart condition. 2. when the s tart condition h as b een tr a n s mitted, the twif fl a g in twcr i s s et, a nd tw s r i s u pd a ted with a s t a t us code indic a ting th a t the s tart condition h as su cce ss - f u lly b een s ent. 3. the a pplic a tion s oftw a re s ho u ld now ex a mine the v a l u e of tw s r, to m a ke su re th a t the s tart condition w as su cce ss f u lly tr a n s mitted. if tw s r indic a te s otherwi s e, the a ppli- c a tion s oftw a re might t a ke s ome s peci a l a ction, like c a lling a n error ro u tine. a ssu ming th a t the s t a t us code i s as expected, the a pplic a tion m us t lo a d s la+w into twdr. remem b er th a t twdr i s us ed b oth for a ddre ss a nd d a t a . after twdr h as b een lo a ded with the de s ired s la+w, a s pecific v a l u e m us t b e written to twcr, in s tr u cting the twi h a rdw a re to tr a n s mit the s la+w pre s ent in twdr. which v a l u e to write i s de s cri b ed l a ter on. however, it i s import a nt th a t the twif b it i s cle a red in the v a l u e writ- ten. the twi will not s t a rt a ny oper a tion as long as the twif b it in twcr i s s et. immedi a tely a fter the a pplic a tion h as cle a red twif, the twi will initi a te tr a n s mi ss ion of the a ddre ss p a cket. 4. when the a ddre ss p a cket h as b een tr a n s mitted, the twif fl a g in twcr i s s et, a nd tw s r i s u pd a ted with a s t a t us code indic a ting th a t the a ddre ss p a cket h as su cce ss - f u lly b een s ent. the s t a t us code will a l s o reflect whether a s l a ve a cknowledged the p a cket or not. 5. the a pplic a tion s oftw a re s ho u ld now ex a mine the v a l u e of tw s r, to m a ke su re th a t the a ddre ss p a cket w as su cce ss f u lly tr a n s mitted, a nd th a t the v a l u e of the ack b it w as as expected. if tw s r indic a te s otherwi s e, the a pplic a tion s oftw a re might t a ke s ome s pe- ci a l a ction, like c a lling a n error ro u tine. a ssu ming th a t the s t a t us code i s as expected, the a pplic a tion m us t lo a d a d a t a p a cket into twdr. subs eq u ently, a s pecific v a l u e m us t b e written to twcr, in s tr u cting the twi h a rdw a re to tr a n s mit the d a t a p a cket pre s ent in twdr. which v a l u e to write i s de s cri b ed l a ter on. however, it i s import a nt th a t the twif b it i s cle a red in the v a l u e written. the twi will not s t a rt a ny oper a tion as start sla+w a data a stop 1. application writes to twcr to initiate transmission of start 2. twif set. status code indicates start condition sent 4. twif set. status code indicates sla+w sent, ack received 6. twif set. status code indicates data sent, ack received 3 . check twsr to see if start was sent. application loads sla+w into twdr, and loads appropriate control signals into twcr, making sure that twif is written to zero and sta is written to zero. 5. check twsr to see if sla+w was sent and ack received. application loads data into twdr, and loads appropriate control signals into twcr, making sure that twif is written to zero. 7. check twsr to see if data was sent and ack received. application loads appropriate control signals to send stop into twcr, making sure that twif is written to zero. twi bus indicates twif set application action twi hardware action
115 3706c?micro?2/11 at89lp3240/6440 long as the twif b it in twcr i s s et. immedi a tely a fter the a pplic a tion h as cle a red twif, the twi will initi a te tr a n s mi ss ion of the d a t a p a cket. 6. when the d a t a p a cket h as b een tr a n s mitted, the twif fl a g in twcr i s s et, a nd tw s r i s u pd a ted with a s t a t us code indic a ting th a t the d a t a p a cket h as su cce ss f u lly b een s ent. the s t a t us code will a l s o reflect whether a s l a ve a cknowledged the p a cket or not. 7. the a pplic a tion s oftw a re s ho u ld now ex a mine the v a l u e of tw s r, to m a ke su re th a t the d a t a p a cket w as su cce ss f u lly tr a n s mitted, a nd th a t the v a l u e of the ack b it w as as expected. if tw s r indic a te s otherwi s e, the a pplic a tion s oftw a re might t a ke s ome s pe- ci a l a ction, like c a lling a n error ro u tine. a ssu ming th a t the s t a t us code i s as expected, the a pplic a tion m us t write a s pecific v a l u e to twcr, in s tr u cting the twi h a rdw a re to tr a n s mit a s top condition. which v a l u e to write i s de s cri b ed l a ter on. however, it i s import a nt th a t the twif b it i s cle a red in the v a l u e written. the twi will not s t a rt a ny oper a tion as long as the twif b it in twcr i s s et. immedi a tely a fter the a pplic a tion h as cle a red twif, the twi will initi a te tr a n s mi ss ion of the s top condition. note th a t twif i s not s et a fter a s top condition h as b een s ent. even tho u gh thi s ex a mple i s s imple, it s how s the principle s involved in a ll twi tr a n s mi ss ion s . the s e c a n b e su mm a rized as follow s : ? when the twi h as fini s hed a n oper a tion a nd expect s a pplic a tion re s pon s e, the twif fl a g i s s et. the s cl line i s p u lled low u ntil twif i s cle a red. ? when the twif fl a g i s s et, the us er m us t u pd a te a ll twi regi s ter s with the v a l u e relev a nt for the next twi bus cycle. a s a n ex a mple, twdr m us t b e lo a ded with the v a l u e to b e tr a n s mitted in the next bus cycle. ?after a ll twi regi s ter u pd a te s a nd other pending a pplic a tion s oftw a re t as k s h a ve b een completed, twcr i s written. when writing twcr, the twif b it s ho u ld b e cle a red. the twi will then commence exec u ting wh a tever oper a tion w as s pecified b y the twcr s etting. 18.6 transmission modes the twi c a n oper a te in one of fo u r m a jor mode s . the s e a re n a med m as ter tr a n s mitter (mt), m as ter receiver (mr), s l a ve tr a n s mitter ( s t) a nd s l a ve receiver ( s r). s ever a l of the s e mode s c a n b e us ed in the sa me a pplic a tion. a s a n ex a mple, the twi c a n us e mt mode to write d a t a into a twi eeprom, mr mode to re a d the d a t a ba ck from the eeprom. if other m as ter s a re pre s ent in the s y s tem, s ome of the s e might tr a n s mit d a t a to the twi, a nd then s r mode wo u ld b e us ed. it i s the a pplic a tion s oftw a re th a t decide s which mode s a re leg a l. the following s ection s de s cri b e e a ch of the s e mode s . po ss i b le s t a t us code s a re de s cri b ed a long with fig u re s det a iling d a t a tr a n s mi ss ion in e a ch of the mode s . the s e fig u re s cont a in the following abb revi a tion s : s : s tart condition r s : repeated s tart condition r: re a d b it (high level a t s da) w: write b it (low level a t s da) a: acknowledge b it (low level a t s da) a : not a cknowledge b it (high level a t s da) d a t a : 8 - b it d a t a b yte p: s top condition
116 3706c?micro?2/11 at89lp3240/6440 s la: s l a ve addre ss in fig u re 1 8 -11 to fig u re 1 8 -14 , circle s a re us ed to indic a te th a t the twif fl a g i s s et. the n u m- b er s in the circle s s how the s t a t us code held in tw s r. at the s e point s , a ction s m us t b e t a ken b y the a pplic a tion to contin u e or complete the twi tr a n s fer. the twi tr a n s fer i s sus pended u ntil the twif fl a g i s cle a red b y s oftw a re. when the twif fl a g i s s et, the s t a t us code in tw s r i s us ed to determine the a ppropri a te s oft- w a re a ction. for e a ch s t a t us code, the req u ired s oftw a re a ction a nd det a il s of the following s eri a l tr a n s fer a re given in t ab le 1 8 -6 to t ab le 1 8 -9 . 18.6.1 master transmitter mode in the m as ter tr a n s mitter mode, a n u m b er of d a t a b yte s a re tr a n s mitted to a s l a ve receiver. in order to enter a m as ter mode, a s tart condition m us t b e tr a n s mitted. the form a t of the follow- ing a ddre ss p a cket determine s whether m as ter tr a n s mitter or m as ter receiver mode i s to b e entered. if s la+w i s tr a n s mitted, mt mode i s entered, if s la+r i s tr a n s mitted, mr mode i s entered. a s tart condition i s s ent b y writing the following v a l u e to twcr: twen m us t b e s et to en ab le the two-wire s eri a l interf a ce, s ta m us t b e written to one to tr a n s - mit a s tart condition a nd twif m us t b e cle a red. the twi will then te s t the two-wire s eri a l b us a nd gener a te a s tart condition as s oon as the bus b ecome s free. after a s tart condi- tion h as b een tr a n s mitted, the twif fl a g i s s et b y h a rdw a re, a nd the s t a t us code in tw s r will b e 0 8 h ( s ee t ab le 1 8 -6 ). in order to enter mt mode, s la+w m us t b e tr a n s mitted. thi s i s done b y writing s la+w to twdr. there a fter the twif b it s ho u ld b e cle a red to contin u e the tr a n s fer. when s la+w h as b een tr a n s mitted a nd a n a cknowledgment b it h as b een received, twif i s s et a g a in a nd a n u m b er of s t a t us code s in tw s r a re po ss i b le. po ss i b le s t a t us code s in m as ter mode a re 1 8 h, 20h, or 3 8 h. the a ppropri a te a ction to b e t a ken for e a ch of the s e s t a t us code s i s det a iled in t ab le 1 8 -6 . after s la+w h as b een su cce ss f u lly tr a n s mitted, a d a t a p a cket s ho u ld b e tr a n s mitted. thi s i s done b y writing the d a t a b yte to twdr. twdr m us t only b e written when twif i s high. if not, the a cce ss will b e di s c a rded a nd the previo us v a l u e will b e tr a n s mitted. after u pd a ting twdr, the twif b it s ho u ld b e cle a red to contin u e the tr a n s fer. thi s s cheme i s repe a ted u ntil the l as t b yte h as b een s ent a nd the tr a n s fer i s ended b y gener a ting a s top condition or a repe a ted s tart condition. a s top condition i s gener a ted b y writing the following v a l u e to twcr: a repeated s tart condition i s gener a ted b y writing the following v a l u e to twcr: after a repe a ted s tart condition ( s t a t us 10h) the two-wire s eri a l interf a ce c a n a cce ss the sa me s l a ve a g a in, or a new s l a ve witho u t tr a n s mitting a s top condition. repe a ted s tart en ab le s the m as ter to s witch b etween s l a ve s , m as ter tr a n s mitter mode a nd m as ter receiver mode witho u t lo s ing control of the bus . twcr ?twen s ta s to twif aa ? ? v a l u e x1100x x x twcr ?twen s ta s to twif aa ? ? v a l u e x1010x x x twcr ?twen s ta s to twif aa ? ? v a l u e x1100x x x
117 3706c?micro?2/11 at89lp3240/6440 . table 18-6. s t a t us code s for m as ter tr a n s mitter mode status code (twsr) status of the two-wire serial bus and two-wire serial interface hardware application software response next action taken by twi hardware to/from twdr to twcr sta sto twif aa 0x0 8 a s tart condition h as b een tr a n s mitted lo a d s la+w 0 0 1 x s la+w will b e tr a n s mitted; ack or not ack will b e received 10h a repe a ted s ta rt condition h as b een tr a n s mitted lo a d s la+w 0 0 1 x s la+w will b e tr a n s mitted; ack or not ack will b e received lo a d s la+r 0 0 1 x s la+r will b e tr a n s mitted; logic will s witch to m as ter receiver mode 1 8 h s la+w h as b een tr a n s mitted; ack h as b een received lo a d d a t a b yte 0 0 1 x d a t a b yte will b e tr a n s mitted a nd ack or not ack will b e received no a ction 1 0 1 x repe a ted s tart will b e tr a n s mitted no a ction 0 1 1 x s top condition will b e tr a n s mitted a nd s to fl a g will b e re s et no a ction 1 1 1 x s top condition followed b y a s tart condition will b e tr a n s mitted a nd s to fl a g will b e re s et 20h s la+w h as b een tr a n s mitted; not ack h as b een received lo a d d a t a b yte 0 0 1 x d a t a b yte will b e tr a n s mitted a nd ack or not ack will b e received no a ction 1 0 1 x repe a ted s tart will b e tr a n s mitted no a ction 0 1 1 x s top condition will b e tr a n s mitted a nd s to fl a g will b e re s et no a ction 1 1 1 x s top condition followed b y a s tart condition will b e tr a n s mitted a nd s to fl a g will b e re s et 2 8 h d a t a b yte h as b een tr a n s mitted; ack h as b een received lo a d d a t a b yte 0 0 1 x d a t a b yte will b e tr a n s mitted a nd ack or not ack will b e received no a ction 1 0 1 x repe a ted s tart will b e tr a n s mitted no a ction 0 1 1 x s top condition will b e tr a n s mitted a nd s to fl a g will b e re s et no a ction 1 1 1 x s top condition followed b y a s tart condition will b e tr a n s mitted a nd s to fl a g will b e re s et 30h d a t a b yte h as b een tr a n s mitted; not ack h as b een received lo a d d a t a b yte 0 0 1 x d a t a b yte will b e tr a n s mitted a nd ack or not ack will b e received no a ctio 1 0 1 x repe a ted s tart will b e tr a n s mitted no a ctio 0 1 1 x s top condition will b e tr a n s mitted a nd s to fl a g will b e re s et no a ctio 1 1 1 x s top condition followed b y a s tart condition will b e tr a n s mitted a nd s to fl a g will b e re s et 3 8 h ar b itr a tion lo s t in s la+w or d a t a b yte s no a ction 0 0 1 x tw o - w i r e s eri a l b us will b e rele as ed a nd not a ddre ss ed s l a ve mode entered no a ction 1 0 1 x a s tart condition will b e tr a n s mitted when the bus b ecome s free
118 3706c?micro?2/11 at89lp3240/6440 figure 18-11. form a t a nd s t a te s in m as ter tr a n s mitter mode 18.6.2 master receiver mode in the m as ter receiver mode, a n u m b er of d a t a b yte s a re received from a s l a ve tr a n s mitter. in order to enter a m as ter mode, a s tart condition m us t b e tr a n s mitted. the form a t of the follow- ing a ddre ss p a cket determine s whether m as ter tr a n s mitter or m as ter receiver mode i s to b e entered. if s la+w i s tr a n s mitted, mt mode i s entered, if s la+r i s tr a n s mitted, mr mode i s entered. s sla w a data a p 08h 18h 28h r sla w 10h ap 20h p 3 0h a or a 3 8h a other master continues a or a 3 8h other master continues r a 68h other master continues 78h b0h to corresponding states in slave mode mt mr successfull transmission to a slave receiver next transfer started with a repeated start condition not acknowledge received after the slave address not acknowledge received after a data byte arbitration lost in slave address or data byte arbitration lost and addressed as slave data a n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in twsr) corresponds to a defined state of the two-wire serial bus. the prescaler bits are zero or masked to zero s
119 3706c?micro?2/11 at89lp3240/6440 twen m us t b e written to one to en ab le the two-wire s eri a l interf a ce, s ta m us t b e written to one to tr a n s mit a s tart condition a nd twif m us t b e cle a red. the twi will then te s t the two- wire s eri a l b us a nd gener a te a s tart condition as s oon as the bus b ecome s free. after a s tart condition h as b een tr a n s mitted, the twif fl a g i s s et b y h a rdw a re, a nd the s t a t us code in tw s r will b e 0 8 h ( s ee t ab le 1 8 -7 ). in order to enter mr mode, s la+r m us t b e tr a n s mitted. thi s i s done b y writing s la+r to twdr. there a fter the twif b it s ho u ld b e cle a red to contin u e the tr a n s fer. when s la+r h as b een tr a n s mitted a nd a n a cknowledgment b it h as b een received, twif i s s et a g a in a nd a n u m b er of s t a t us code s in tw s r a re po ss i b le. po ss i b le s t a t us code s in m as ter mode a re 3 8 h, 40h or 4 8 h. the a ppropri a te a ction to b e t a ken for e a ch of the s e s t a t us code s i s det a iled in t ab le 1 8 -7 . received d a t a c a n b e re a d from the twdr regi s ter when the twif fl a g i s s et high b y h a rdw a re. thi s s cheme i s repe a ted u ntil the l as t b yte h as b een received. after the l as t b yte h as b een received, the mr s ho u ld inform the s t b y s ending a nack a fter the l as t received d a t a b yte. the tr a n s fer i s ended b y gener a ting a s top condition or a repe a ted s tart condition. table 18-7. s t a t us code s for m as ter receiver mode status code (twsr) status of the two-wire serial bus and two-wire serial interface hardware application software response next action taken by twi hardware to/from twdr to twcr sta sto twif aa 0 8 h a s tart condition h as b een tr a n s mitted lo a d s la+r 0 0 1 x s la+r will b e tr a n s mitted; ack or not ack will b e received 10h a repe a ted s ta rt condition h as b een tr a n s mitted lo a d s la+r 0 0 1 x s la+r will b e tr a n s mitted; ack or not ack will b e received lo a d s la+w 0 0 1 x s la+w will b e tr a n s mitted; logic will s witch to m as ter tr a n s mitter mode 3 8 h ar b itr a tion lo s t in s la+r or not ack b it no a ction 0 0 1 x tw o - w i r e s eri a l b us will b e rele as ed a nd not a ddre ss ed s l a ve mode will b e entered no a ction 1 0 1 x a s tart condition will b e tr a n s mitted when the bus b ecome s free 40h s la+r h as b een tr a n s mitted; ack h as b een received no a ction 0 0 1 0 d a t a b yte will b e received a nd not ack will b e ret u rned no a ction 0 0 1 1 d a t a b yte will b e received a nd ack will b e ret u rned 4 8 h s la+r h as b een tr a n s mitted; not ack h as b een received no a ction 1 0 1 x repe a ted s tart will b e tr a n s mitted no a ction 0 1 1 x s top condition will b e tr a n s mitted a nd s to fl a g will b e re s et no a ction 1 1 1 x s top condition followed b y a s tart condition will b e tr a n s mitted a nd s to fl a g will b e re s et 50h d a t a b yte h as b een received; ack h as b een ret u rned re a d d a t a b yte 0 0 1 0 d a t a b yte will b e received a nd not ack will b e ret u rned re a d d a t a b yte 0 0 1 1 d a t a b yte will b e received a nd ack will b e ret u rned 5 8 h d a t a b yte h as b een received; not ack h as b een ret u rned re a d d a t a b yte 1 0 1 x repe a ted s tart will b e tr a n s mitted re a d d a t a b yte 0 1 1 x s top condition will b e tr a n s mitted a nd s to fl a g will b e re s et re a d d a t a b yte 1 1 1 x s top condition followed b y a s tart condition will b e tr a n s mitted a nd s to fl a g will b e re s et
120 3706c?micro?2/11 at89lp3240/6440 figure 18-12. form a t a nd s t a te s in m as ter receiver mode 18.6.3 slave receiver mode in the s l a ve receiver mode, a n u m b er of d a t a b yte s a re received from a m as ter tr a n s mitter. to initi a te the s l a ve receiver mode, twar a nd twcr m us t b e initi a lized as follow s : the u pper s even b it s a re the a ddre ss to which the two-wire s eri a l interf a ce will re s pond when a ddre ss ed b y a m as ter. if the l s b i s s et, the twi will re s pond to the gener a l c a ll a ddre ss (00h), otherwi s e it will ignore the gener a l c a ll a ddre ss .: s sla r a data a 08h 40h 50h sla r 10h ap 48h a or a 3 8h other master continues 3 8h other master continues w a 68h other master continues 78h b0h to corresponding states in slave mode mr mt successfull reception from a slave receiver next transfer started with a repeated start condition not acknowledge received after the slave address arbitration lost in slave address or data byte arbitration lost and addressed as slave data a n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in twsr) corresponds to a defined state of the two-wire serial bus. the prescaler bits are zero or masked to zero p data a 58h a r s twar twa6 twa5 twa4 twa3 twa2 twa1 twa0 gc v a l u edevice? s own s l a ve addre ss x twcr ?twen s ta s to twif aa ? ? v a l u e x10001 x x
121 3706c?micro?2/11 at89lp3240/6440 twen m us t b e written to one to en ab le the twi. the aa b it m us t b e written to one to en ab le the a cknowledgment of the device? s own s l a ve a ddre ss or the gener a l c a ll a ddre ss . s ta a nd s to m us t b e written to zero. when twar a nd twcr h a ve b een initi a lized, the twi w a it s u ntil it i s a ddre ss ed b y it s own s l a ve a ddre ss (or the gener a l c a ll a ddre ss if en ab led) followed b y the d a t a direction b it. if the direction b it i s ?0? (write), the twi will oper a te in s r mode, otherwi s e s t mode i s entered. after it s own s l a ve a ddre ss a nd the write b it h a ve b een received, the twif fl a g i s s et a nd a v a lid s t a - t us code c a n b e re a d from tw s r. the s t a t us code i s us ed to determine the a ppropri a te s oftw a re a ction. the a ppropri a te a ction to b e t a ken for e a ch s t a t us code i s det a iled in t ab le 1 8 - 8 . the s l a ve receiver mode m a y a l s o b e entered if a r b itr a tion i s lo s t while the twi i s in the m as - ter mode ( s ee s t a te s 6 8 h a nd 7 8 h). if the aa b it i s re s et d u ring a tr a n s fer, the twi will ret u rn a ?not acknowledge? (?1?) to s da a fter the next received d a t a b yte. thi s c a n b e us ed to indic a te th a t the s l a ve i s not ab le to receive a ny more b yte s . while aa i s zero, the twi doe s not a cknowledge it s own s l a ve a ddre ss . however, the two-wire s eri a l b us i s s till monitored a nd a ddre ss recognition m a y re su me a t a ny time b y s etting aa. thi s implie s th a t the aa b it m a y b e us ed to tempor a rily i s ol a te the twi from the two- wire s eri a l b us . . table 18-8. s t a t us code s for s l a ve receiver mode status code (twsr) status of the two-wire serial bus and two-wire serial interface hardware application software response next action taken by twi hardware to/from twdr to twcr sta sto twif aa 60h own s la+w h as b een received; ack h as b een ret u rned no a ction x 0 1 0 d a t a b yte will b e received a nd not ack will b e ret u rned no a ction x 0 1 1 d a t a b yte will b e received a nd ack will b e ret u rned 6 8 h ar b itr a tion lo s t in s la+r/w as m as ter; own s la+w h as b een received; ack h as b een ret u rned no a ction x 0 1 0 d a t a b yte will b e received a nd not ack will b e ret u rned no a ction x 0 1 1 d a t a b yte will b e received a nd ack will b e ret u rned 70h gener a l c a ll a ddre ss h as b een received; ack h as b een ret u rned no a ction x 0 1 0 d a t a b yte will b e received a nd not ack will b e ret u rned no a ction x 0 1 1 d a t a b yte will b e received a nd ack will b e ret u rned 7 8 h ar b itr a tion lo s t in s la+r/w as m as ter; gener a l c a ll a ddre ss h as b een received; ack h as b een ret u rned no a ction x 0 1 0 d a t a b yte will b e received a nd not ack will b e ret u rned no a ction x 0 1 1 d a t a b yte will b e received a nd ack will b e ret u rned 8 0h previo us ly a ddre ss ed with own s la+w; d a t a h as b een received; ack h as b een ret u rned re a d d a t a b yte x 0 1 0 d a t a b yte will b e received a nd not ack will b e ret u rned re a d d a t a b yte x 0 1 1 d a t a b yte will b e received a nd ack will b e ret u rned
122 3706c?micro?2/11 at89lp3240/6440 figure 18-13. form a t a nd s t a te s in s l a ve receiver mode 88 h previo us ly a ddre ss ed with own s la+w; d a t a h as b een received; not ack h as b een ret u rned re a d d a t a b yte 0 0 1 0 s witched to the not a ddre ss ed s l a ve mode; no recognition of own s la or gca re a d d a t a b yte 0 0 1 1 s witched to the not a ddre ss ed s l a ve mode; own s la will b e recognized; gca will b e recognized if gc = ?1? re a d d a t a b yte 1 0 1 0 s witched to the not a ddre ss ed s l a ve mode; no recognition of own s la or gca; a s ta rt condition will b e tr a n s mitted when the bus b ecome s free re a d d a t a b yte 1 0 1 1 s witched to the not a ddre ss ed s l a ve mode; own s la will b e recognized; gca will b e recognized if gc = ?1?; a s tart condition will b e tr a n s mitted when the bus b ecome s free 90h previo us ly a ddre ss ed with gener a l c a ll; d a t a h as b een received; ack h as b een ret u rned re a d d a t a b yte x 0 1 0 d a t a b yte will b e received a nd not ack will b e ret u rned re a d d a t a b yte x 0 1 1 d a t a b yte will b e received a nd ack will b e ret u rned 9 8 h previo us ly a ddre ss ed with gener a l c a ll; d a t a h as b een received; not ack h as b een ret u rned re a d d a t a b yte 0 0 1 0 s witched to the not a ddre ss ed s l a ve mode; no recognition of own s la or gca re a d d a t a b yte 0 0 1 1 s witched to the not a ddre ss ed s l a ve mode; own s la will b e recognized; gca will b e recognized if gc = ?1? re a d d a t a b yte 1 0 1 0 s witched to the not a ddre ss ed s l a ve mode; no recognition of own s la or gca; a s ta rt condition will b e tr a n s mitted when the bus b ecome s free re a d d a t a b yte 1 0 1 1 s witched to the not a ddre ss ed s l a ve mode; own s la will b e recognized; gca will b e recognized if gc = ?1?; a s tart condition will b e tr a n s mitted when the bus b ecome s free a0h a s top condition or repe a ted s tart condition h as b een received while s till a ddre ss ed as s l a ve no action 0 0 1 0 s witched to the not a ddre ss ed s l a ve mode; no recognition of own s la or gca no action 0 0 1 1 s witched to the not a ddre ss ed s l a ve mode; own s la will b e recognized; gca will b e recognized if gc = ?1? no action 1 0 1 0 s witched to the not a ddre ss ed s l a ve mode; no recognition of own s la or gca; a s ta rt condition will b e tr a n s mitted when the bus b ecome s free no action 1 0 1 1 s witched to the not a ddre ss ed s l a ve mode; own s la will b e recognized; gca will b e recognized if gc = ?1?; a s tart condition will b e tr a n s mitted when the bus b ecome s free table 18-8. s t a t us code s for s l a ve receiver mode s sla w a data a 60h 80h 88h a reception of the own slave address and one or more data bytes. all are acknowledged last data byte received is not acknowledged arbitration lost as master and addressed as slave p or s data a 80h a0h p or s a
123 3706c?micro?2/11 at89lp3240/6440 18.6.4 slave transmitter mode in the s l a ve tr a n s mitter mode, a n u m b er of d a t a b yte s a re tr a n s mitted to a m as ter receiver. to initi a te the s l a ve tr a n s mitter mode, u pper 7 b it s of twar m us t b e initi a lized with the a ddre ss to which the two-wire s eri a l interf a ce will re s pond when a ddre ss ed b y a m as ter. if the l s b i s s et, the twi will re s pond to the gener a l c a ll a ddre ss (00h), otherwi s e it will ignore the gener a l c a ll a ddre ss . twen m us t b e written to one to en ab le the twi. the aa b it m us t b e written to one to en ab le the a cknowledgment of the device? s own s l a ve a ddre ss or the gener a l c a ll a ddre ss . s ta a nd s to m us t b e written to zero. when twar a nd twcr h a ve b een initi a lized, the twi w a it s u ntil it i s a ddre ss ed b y it s own s l a ve a ddre ss (or the gener a l c a ll a ddre ss if en ab led) followed b y the d a t a direction b it. if the direction b it i s ?1? (re a d), the twi will oper a te in s t mode, otherwi s e s r mode i s entered. after it s own s l a ve a ddre ss a nd the write b it h a ve b een received, the twint fl a g i s s et a nd a v a lid s t a t us code c a n b e re a d from tw s r. the s t a t us code i s us ed to determine the a ppropri a te s oft- w a re a ction. the a ppropri a te a ction to b e t a ken for e a ch s t a t us code i s det a iled in t ab le 1 8 -9 . the s l a ve tr a n s mitter mode m a y a l s o b e entered if a r b itr a tion i s lo s t while the twi i s in the m as ter mode ( s ee s t a te b0h). if the aa b it i s written to zero d u ring a tr a n s fer, the twi will tr a n s mit the l as t b yte of the tr a n s fer. s t a te c0h or s t a te c 8 h will b e entered, depending on whether the m as ter receiver tr a n s mit s a nack or ack a fter the fin a l b yte. the twi i s s witched to the not a ddre ss ed s l a ve mode, a nd will ignore the m as ter if it contin u e s the tr a n s fer. th us the m as ter receiver receive s a ll ?1 s ? as s eri a l d a t a . s t a te c 8 h i s entered if the m as ter dem a nd s a ddition a l d a t a b yte s ( b y tr a n s mitting ack), even tho u gh the s l a ve h as tr a n s mitted the l as t b yte (aa zero a nd expecting nack from the m as ter). while aa i s zero, the twi doe s not re s pond to it s own s l a ve a ddre ss . however, the two-wire s eri a l b us i s s till monitored a nd a ddre ss recognition m a y re su me a t a ny time b y s et- ting aa. thi s implie s th a t the aa b it m a y b e us ed to tempor a rily i s ol a te the twi from the two- wire s eri a l b us . figure 18-14. form a t a nd s t a te s in s l a ve tr a n s mitter mode s sla r a data a a8h b8h a b0h reception of the own slave address and one or more data bytes last data byte transmitted. switched to not addressed slave (twea = '0') arbitration lost as master and addressed as slave n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in twsr) corresponds to a defined state of the two-wire serial bus. the prescaler bits are zero or masked to zero p or s data c0h data a a c8h p or s all 1's a
124 3706c?micro?2/11 at89lp3240/6440 . table 18-9. s t a t us code s for s l a ve tr a n s mitter mode status code (twsr) status of the two-wire serial bus and two-wire serial interface hardware application software response next action taken by twi hardware to/from twdr to twcr sta sto twif aa a 8 h own s la+r h as b een received; ack h as b een ret u rned lo a d d a t a b yte x 0 1 0 l as t d a t a b yte will b e tr a n s mitted a nd not ack s ho u ld b e received lo a d d a t a b yte x 0 1 1 d a t a b yte will b e tr a n s mitted a nd ack s ho u ld b e received b0h ar b itr a tion lo s t in s la+r/w as m as ter; own s la+r h as b een received; ack h as b een ret u rned lo a d d a t a b yte x 0 1 0 l as t d a t a b yte will b e tr a n s mitted a nd not ack s ho u ld b e received lo a d d a t a b yte x 0 1 1 d a t a b yte will b e tr a n s mitted a nd ack s ho u ld b e received b 8 h d a t a b yte in twdr h as b een tr a n s mitted; ack h as b een received lo a d d a t a b yte x 0 1 0 l as t d a t a b yte will b e tr a n s mitted a nd not ack s ho u ld b e received lo a d d a t a b yte x 0 1 1 d a t a b yte will b e tr a n s mitted a nd ack s ho u ld b e received c0h d a t a b yte in twdr h as b een tr a n s mitted; not ack h as b een received no a ction 0 0 1 0 s witched to the not a ddre ss ed s l a ve mode; no recognition of own s la or gca no a ction 0 0 1 1 s witched to the not a ddre ss ed s l a ve mode; own s la will b e recognized; gca will b e recognized if gc = ?1? no a ction 1 0 1 0 s witched to the not a ddre ss ed s l a ve mode; no recognition of own s la or gca; a s ta rt condition will b e tr a n s mitted when the bus b ecome s free no a ction 1 0 1 1 s witched to the not a ddre ss ed s l a ve mode; own s la will b e recognized; gca will b e recognized if gc = ?1?; a s tart condition will b e tr a n s mitted when the bus b ecome s free c 8 h l as t d a t a b yte in twdr h as b een tr a n s mitted (aa = ?0?); ack h as b een received no a ction 0 0 1 0 s witched to the not a ddre ss ed s l a ve mode; no recognition of own s la or gca no a ction 0 0 1 1 s witched to the not a ddre ss ed s l a ve mode; own s la will b e recognized; gca will b e recognized if gc = ?1? no a ction 1 0 1 0 s witched to the not a ddre ss ed s l a ve mode; no recognition of own s la or gca; a s ta rt condition will b e tr a n s mitted when the bus b ecome s free no a ction 1 0 1 1 s witched to the not a ddre ss ed s l a ve mode; own s la will b e recognized; gca will b e recognized if gc = ?1?; a s tart condition will b e tr a n s mitted when the bus b ecome s free
125 3706c?micro?2/11 at89lp3240/6440 18.6.5 miscellaneous states there a re two s t a t us code s th a t do not corre s pond to a defined twi s t a te, s ee t ab le 1 8 -10 . s t a t us f 8 h indic a te s th a t no relev a nt inform a tion i s a v a il ab le b ec aus e the twif fl a g i s not s et. thi s occ u r s b etween other s t a te s , a nd when the twi i s not involved in a s eri a l tr a n s fer. s t a t us 00h indic a te s th a t a bus error h as occ u rred d u ring a two-wire s eri a l b us tr a n s fer. a bus error occ u r s when a s tart or s top condition occ u r s a t a n illeg a l po s ition in the form a t fr a me. ex a mple s of su ch illeg a l po s ition s a re d u ring the s eri a l tr a n s fer of a n a ddre ss b yte, a d a t a b yte, or a n a cknowledge b it. when a bus error occ u r s , twif i s s et. to recover from a bus error, the s to fl a g m us t s et a nd twif m us t b e cle a red. thi s c aus e s the twi to enter the not a ddre ss ed s l a ve mode a nd to cle a r the s to fl a g (no other b it s in twcr a re a ffected). the s da a nd s cl line s a re rele as ed, a nd no s top condition i s tr a n s mitted. 18.6.6 combining several twi modes in s ome c as e s , s ever a l twi mode s m us t b e com b ined in order to complete the de s ired a ction. con s ider for ex a mple re a ding d a t a from a s eri a l eeprom. typic a lly, su ch a tr a n s fer involve s the following s tep s : 1. the tr a n s fer m us t b e initi a ted. 2. the eeprom m us t b e in s tr u cted wh a t loc a tion s ho u ld b e re a d. 3. the re a ding m us t b e performed. 4. the tr a n s fer m us t b e fini s hed. note th a t d a t a i s tr a n s mitted b oth from m as ter to s l a ve a nd vice ver sa . the m as ter m us t in s tr u ct the s l a ve wh a t loc a tion it w a nt s to re a d, req u iring the us e of the mt mode. subs eq u ently, d a t a m us t b e re a d from the s l a ve, implying the us e of the mr mode. th us , the tr a n s fer direction m us t b e ch a nged. the m as ter m us t keep control of the bus d u ring a ll the s e s tep s , a nd the s tep s s ho u ld b e c a rried o u t as a n a tomic oper a tion. if thi s principle i s viol a ted in a m u lti-m as ter s y s - tem, a nother m as ter c a n a lter the d a t a pointer in the eeprom b etween s tep s 2 a nd 3, a nd the m as ter will re a d the wrong d a t a loc a tion. su ch a ch a nge in tr a n s fer direction i s a ccompli s hed b y tr a n s mitting a repeated s tart b etween the tr a n s mi ss ion of the a ddre ss b yte a nd reception of the d a t a . after a repeated s tart, the m as ter keep s owner s hip of the bus . the following fig u re s how s the flow in thi s tr a n s fer. table 18-10. mi s cell a neo us s t a te s status code (twsr) status of the two-wire serial bus and two-wire serial interface hardware application software response next action taken by twi hardware to/from twdr to twcr sta sto twif aa f 8 h no relev a nt s t a te inform a tion a v a il ab le; twif = ?0? no a ction no a ction w a it or proceed c u rrent tr a n s fer 00h b us error d u e to a n illeg a l s ta rt o r s top condition no a ction 0 1 1 x only the intern a l h a rdw a re i s a ffected, no s top condition i s s ent on the bus . in a ll c as e s , the bus i s rele as ed a nd s to i s cle a red.
126 3706c?micro?2/11 at89lp3240/6440 figure 18-15. com b ining s ever a l twi mode s to acce ss a s eri a l eeprom 19. dual analog comparators the at 8 9lp3240/6440 provide s two a n a log comp a r a tor s . the a n a log comp a r a tor s h a ve the fol- lowing fe a t u re s : ? intern a l 3-level volt a ge reference (1.2v, 1.3v, 1.4v) ?fo u r s h a red an a log inp u t ch a nnel s ? config u re as m u ltiple inp u t window comp a r a tor ? s elect ab le interr u pt condition s ? high- or low-level ?ri s ing- or f a lling-edge ?o u tp u t toggle ?h a rdw a re de b o u ncing mode s figure 19-1. d ua l comp a r a tor block di a gr a m a b lock di a gr a m of the d ua l a n a log comp a r a tor s with relev a nt connection s i s s hown in fig u re 19-1 . inp u t option s a llow the comp a r a tor s to f u nction in a n u m b er of different config u r a tion s as s hown in fig u re 19-4 . comp a r a tor oper a tion i s su ch th a t the o u tp u t i s a logic ?1? when the po s i- tive inp u t i s gre a ter th a n the neg a tive inp u t. otherwi s e the o u tp u t i s a zero. s etting the cena (ac s ra.3) a nd cenb (ac s rb.3) b it s en ab le comp a r a tor a a nd b re s pectively. the us er m us t m as ter tr a n s mitter m as ter receiver s = s tart r s = repeated s tart p = s top tr a n s mitted from m as ter to s l a ve tr a n s mitted from s l a ve to m as ter s s la+w a addre ss a r s s la+r a data a p a b (p2.5) ain1 (p2.6) ain2 (p2.4) ain0 (p2.7) ain 3 11 10 01 00 11 10 01 00 rfb1 rfb0 rfa1 rfa0 11 10 01 00 11 10 01 00 csb0 csb1 csa0 csa1 cmpb (p4.7) cmpa (p4.6) cmb0 cmb1 cmb2 cma0 cma1 cma2 cfb cfa ec interrupt v aref v aref- v aref+
127 3706c?micro?2/11 at89lp3240/6440 a l s o s et the cona (ac s ra.5) or conb (ac s rb.5) b it s to connect the comp a r a tor inp u t s b efore us ing a comp a r a tor. when a comp a r a tor i s fir s t en ab led, the comp a r a tor o u tp u t a nd inter- r u pt fl a g a re not g ua r a nteed to b e s t ab le for 10 s . the corre s ponding comp a r a tor interr u pt s ho u ld not b e en ab led d u ring th a t time, a nd the comp a r a tor interr u pt fl a g m us t b e cle a red b efore the interr u pt i s en ab led in order to prevent a n immedi a te interr u pt s ervice. before en ab ling the comp a r a tor s , the a n a log inp u t s s ho u ld b e tri s t a ted b y p u tting p2.4, p2.5, p2.6 a nd p2.7 into inp u t-only mode. s ee ?port an a log f u nction s ? on p a ge 4 8 . e a ch comp a r a tor m a y b e config u red to c aus e a n interr u pt u nder a v a riety of o u tp u t v a l u e condi- tion s b y s etting the cm x 2-0 b it s in ac s r x . the comp a r a tor interr u pt fl a g s cf x in ac s r x a re s et whenever the comp a r a tor o u tp u t s m a tch the condition s s pecified b y cm x 2-0. the fl a g s m a y b e polled b y s oftw a re or m a y b e us ed to gener a te a n interr u pt a nd m us t b e cle a red b y s oftw a re. both comp a r a tor s s h a re a common interr u pt vector. if b oth comp a r a tor s a re en ab led, the us er need s to re a d the fl a g s a fter entering the interr u pt s ervice ro u tine to determine which comp a r a - tor c aus ed the interr u pt. the cac 1-0 a nd cbc 1-0 b it s in aref control when the comp a r a tor interr u pt s sa mple the com- p a r a tor o u tp u t s . norm a lly the o u tp u t s a re sa mpled every clock s y s tem; however, the o u tp u t s m a y a l s o b e sa mpled whenever timer 0, timer 1 or timer 2 overflow s . the s e s etting s a llow the comp a r a tor s to b e sa mpled a t a s pecific time or to red u ce the n u m b er of comp a r a tor event s s een b y the s y s tem when us ing level s en s itive mode s . the comp a r a tor s will contin u e to f u nction d u ring idle mode. if thi s i s not the de s ired b eh a vior, the comp a r a tor s s ho u ld b e di sab led b efore entering idle. the comp a r a tor s a re a lw a y s di sab led d u ring power-down mode. 19.1 analog input muxes the po s itive inp u t termin a l of e a ch comp a r a tor m a y b e connected to a ny of the fo u r a n a log inp u t pin s b y ch a nging the c s a 1-0 or c s b 1-0 b it s in ac s ra a nd ac s rb. when ch a nging the a n a log inp u t pin s , the comp a r a tor m us t b e di s connected from it s inp u t s b y cle a ring the cona or conb b it s . the connection i s re s tored b y s etting the b it s a g a in a fter the m u xe s h a ve b een modified. clr ec ; disable comparator interrupts anl acsra, #0dfh ; clear cona to disconnect comp a ... ; modify csa or rfa bits orl acsra, #020h ; set cona to connect comp a anl acsra, #0efh ; clear any spurious interrupt setb ec ; re-enable comparator interrupts the corre s ponding comp a r a tor interr u pt s ho u ld not b e en ab led while the inp u t s a re b eing ch a nged, a nd the comp a r a tor interr u pt fl a g m us t b e cle a red b efore the interr u pt i s re-en ab led in order to prevent a n u nintention a l interr u pt req u e s t. the eq u iv a lent model for the a n a log inp u t circ u itry i s ill us tr a ted in fig u re 20-3 . an a n a log s o u rce a pplied to ainn i s sub jected to the pin c a p a cit a nce a nd inp u t le a k a ge of th a t pin, reg a rdle ss of whether th a t ch a nnel i s s elected as inp u t to the comp a r a tor. when the ch a nnel i s s elected, the s o u rce m us t drive the inp u t c a p a cit a nce of the comp a r a tor thro u gh the s erie s re s i s t a nce (com- b ined re s i s t a nce in the inp u t p a th).
128 3706c?micro?2/11 at89lp3240/6440 figure 19-2. eq u iv a lent an a log inp u t model 19.2 internal reference voltage the neg a tive inp u t termin a l of e a ch comp a r a tor m a y b e connected to a n intern a l volt a ge refer- ence b y ch a nging the rfb 1-0 or rfa 1-0 b it s in aref. the intern a l reference volt a ge, v aref , i s s et to 1.3 v 5%. the volt a ge reference a l s o provide s two a ddition a l volt a ge level s a pproxi- m a tely 100 mv ab ove a nd b elow v aref . the s e level s m a y b e us ed to config u re the comp a r a tor s as a n intern a lly referenced window comp a r a tor with u p to fo u r inp u t ch a nnel s . ch a nging the ref- erence inp u t m us t follow the sa me ro u tine us ed for ch a nging the po s itive inp u t as de s cri b ed in ?an a log inp u t m u xe s ? ab ove. 19.3 comparator interrupt debouncing the comp a r a tor o u tp u t i s norm a lly sa mpled every clock cycle. the condition s on the a n a log inp u t s m a y b e su ch th a t the comp a r a tor o u tp u t will toggle exce ss ively. thi s i s e s peci a lly tr u e if a pplying s low moving a n a log inp u t s . three de b o u ncing mode s a re provided to filter o u t thi s noi s e for edge-triggered interr u pt s . in de b o u ncing mode, the comp a r a tor us e s timer 1 to mod u - l a te it s sa mpling time when c x c 1-0 = 00b. when a relev a nt tr a n s ition occ u r s , the comp a r a tor w a it s u ntil two timer 1 overflow s h a ve occ u rred b efore re sa mpling the o u tp u t. if the new sa mple a gree s with the expected v a l u e, cf x i s s et. otherwi s e, the event i s ignored. the filter m a y b e t u ned b y a dj us ting the time-o u t period of timer 1. bec aus e timer 1 i s free r u nning, the de b o u ncer m us t w a it for two overflow s to g ua r a ntee th a t the sa mpling del a y i s a t le as t 1 time-o u t period. therefore, a fter the initi a l edge event, the interr u pt m a y occ u r b etween 1 a nd 2 time-o u t period s l a ter. s ee fig u re 19-3 . when the comp a r a tor clock i s provided b y one of the timer over- flow s , i.e. c x c 1-0 != 00b, a ny ch a nge in the comp a r a tor o u tp u t m us t b e v a lid a fter 4 sa mple s to b e a ccepted as a n edge event. figure 19-3. neg a tive edge with de b o u ncing ex a mple ainn c cmp < 0. 3 pf r in = 10 k c pin = 10 pf r mux = 10 k comp a r a tor o u t timer 1 overflow cfx s t a rt s t a rt comp a re (rejected) comp a re ( a ccepted)
129 3706c?micro?2/11 at89lp3240/6440 figure 19-4. d ua l comp a r a tor config u r a tion ex a mple s a. dual independent comparators with external references + - a cmpa ain0 ain1 + - b cmpb ain 3 ain2 csa = 00 rfa = 00 csb = 11 rfb = 00 b. 3 -channel comparator with external reference + - a cmpa ain0 ain1 csa = 00/10/11 rfa = 00 ain2 ain 3 c. 4-channel comparator with internal reference + - a cmpa ain0 v aref csa = 00/01/10/11 rfa = 10 ain1 ain2 ain 3 d. 2-channel comparator with internal reference & comparator with external reference + - a cmpa ain0 v aref csa = 00/01 rfa = 10 ain1 + - b cmpb ain 3 ain2 csb = 11 rfb = 00 e. 2-channel comparator with external reference & comparator with internal reference + - a cmpa ain0 v aref csa = 00/10 rfa = 00 ain1 + - b cmpb ain2 ain 3 csb = 11 rfb = 10 + - b cmpb + - a cmpa ain1 ain2 ain0 ain 3 csa = csb = 00/11 rfa = rfb = 00 f. 2-channel window comparator with external reference + - b cmpb + - a cmpa ain 3 ain0 ain1 ain2 csa = csb = 00/01/10/11 rfa = 01 rfb = 11 g. 4-channel window comparator with internal reference v aref+ v aref-
130 3706c?micro?2/11 at89lp3240/6440 note s :1.cona m us t b e cle a red to 0 b efore ch a nging c s a[1-0]. 2. de b o u ncing mode s req u ire the us e of timer 1 to gener a te the sa mpling del a y. table 19-1. ac s ra ? an a log comp a r a tor a control & s t a t us regi s ter ac s ra = 97h re s et v a l u e = 0000 0000b not bit addre ssab le c s a1 c s a0 cona cfa cena cma2 cma1 cma0 bit76543210 symbol function c s a [1-0] comp a r a tor a po s itive inp u t ch a nnel s elect (1) csa1 csa0 a+ channel 0 0 ain0 (p2.4) 0 1 ain1 (p2.5) 1 0 ain2 (p2.6) 1 1 ain3 (p2.7) cona comp a r a tor a inp u t connect. when cona = 1 the a n a log inp u t pin s a re connected to the comp a r a tor. when cona = 0 the a n a log inp u t pin s a re di s connected from the comp a r a tor. cona m us t b e cle a red to 0 b efore ch a nging c s a[1-0] or rfa[1-0]. cfa comp a r a tor a interr u pt fl a g. s et when the comp a r a tor o u tp u t meet s the condition s s pecified b y the cma [2-0] b it s a nd cena i s s et. the fl a g m us t b e cle a red b y s oftw a re. the interr u pt m a y b e en ab led/di sab led b y s etting/cle a ring b it 6 of ie. cena comp a r a tor a en ab le. s et thi s b it to en ab le the comp a r a tor. cle a ring thi s b it will force the comp a r a tor o u tp u t low a nd prevent f u rther event s from s etting cfa. when cena = 1 the a n a log inp u t pin s , p2.4?p2.7, h a ve their digit a l inp u t s di sab led if they a re config u red in inp u t-only mode. cma [2-0] comp a r a tor a interr u pt mode cma2 cma1 cma0 interrupt mode 000neg a tive (low) level 001po s itive edge 010toggle with de b o u ncing (2) 011po s itive edge with de b o u ncing (2) 100neg a tive edge 101toggle 110neg a tive edge with de b o u ncing (2) 111po s itive (high) level
131 3706c?micro?2/11 at89lp3240/6440 note s :1.conb m us t b e cle a red to 0 b efore ch a nging c s b[1-0]. 2. de b o u ncing mode s req u ire the us e of timer 1 to gener a te the sa mpling del a y. table 19-2. ac s rb ? an a log comp a r a tor b control & s t a t us regi s ter ac s rb = 9fh re s et v a l u e = 1100 0000b not bit addre ssab le c s b1 c s b0 conb cfb cenb cmb2 cmb1 cmb0 bit76543210 symbol function c s b [1-0] comp a r a tor b po s itive inp u t ch a nnel s elect (1) csb1 csb0 b+ channel 0 0 ain0 (p2.4) 0 1 ain1 (p2.5) 1 0 ain2 (p2.6) 1 1 ain3 (p2.7) conb comp a r a tor b inp u t connect. when conb = 1 the a n a log inp u t pin s a re connected to the comp a r a tor. when conb = 0 the a n a log inp u t pin s a re di s connected from the comp a r a tor. conb m us t b e cle a red to 0 b efore ch a nging c s b[1-0] or rfb[1-0]. cfb comp a r a tor b interr u pt fl a g. s et when the comp a r a tor o u tp u t meet s the condition s s pecified b y the cmb [2-0] b it s a nd cenb i s s et. the fl a g m us t b e cle a red b y s oftw a re. the interr u pt m a y b e en ab led/di sab led b y s etting/cle a ring b it 6 of ie. cenb comp a r a tor b en ab le. s et thi s b it to en ab le the comp a r a tor. cle a ring thi s b it will force the comp a r a tor o u tp u t low a nd prevent f u rther event s from s etting cfb. when cenb = 1 the a n a log inp u t pin s , p2.4?p2.7, h a ve their digit a l inp u t s di sab led if they a re config u red in inp u t-only mode. cmb [2-0] comp a r a tor b interr u pt mode cmb2 cmb1 cmb0 interrupt mode 000neg a tive (low) level 001po s itive edge 010toggle with de b o u ncing (2) 011po s itive edge with de b o u ncing (2) 100neg a tive edge 101toggle 110neg a tive edge with de b o u ncing (2) 111po s itive (high) level
132 3706c?micro?2/11 at89lp3240/6440 note s :1.conb (ac s rb.5) m us t b e cle a red to 0 b efore ch a nging rfb[1-0]. 2. cona (ac s ra.5) m us t b e cle a red to 0 b efore ch a nging rfa[1-0]. table 19-3. aref ? an a log comp a r a tor reference control regi s ter aref = afh re s et v a l u e = 0000 0000b not bit addre ssab le cbc1 cbc0 rfb1 rfb0 cac1 cac0 rfa1 rfa0 bit76543210 symbol function c s c [1-0] comp a r a tor b clock s elect cbc1 cbc0 clock source 00 s y s tem clock 0 0 timer 0 overflow 0 1 timer 1 overflow 0 1 timer 2 overflow rfb [1-0] comp a r a tor b neg a tive inp u t ch a nnel s elect (1) crf1 rfb0 b- channel 0 0 ain2 (p2.6) 0 0 intern a l v aref- ( ~ 1.2v) 0 1 intern a l v aref ( ~ 1.3v) 0 1 intern a l v aref+ ( ~ 1.4v) cac [1-0] comp a r a tor a clock s elect cac1 cac0 clock source 00 s y s tem clock 0 0 timer 0 overflow 0 1 timer 1 overflow 0 1 timer 2 overflow rfa [1-0] comp a r a tor a neg a tive inp u t ch a nnel s elect (2) rfa1 rfa0 a- channel 0 0 ain1 (p2.5) 0 0 intern a l v aref- ( ~ 1.2v) 0 1 intern a l v aref ( ~ 1.3v) 0 1 intern a l v aref+ ( ~ 1.4v)
133 3706c?micro?2/11 at89lp3240/6440 20. digital-to-analog/analog-to-digital converter the at 8 9lp3240/6440 incl u de s a 10- b it d a t a converter (dadc) with the following fe a t u re s : ? digit a l-to-an a log (dac) or an a log-to-digit a l (adc) mode ?10- b it re s ol u tion ? 6.5 s conver s ion time ? 8 m u ltiplexed s ingle-ended ch a nnel s or 4 differenti a l ch a nnel s ? s elect ab le 1.0v10% intern a l reference volt a ge ?option a l left-adj us t of conver s ion re su lt s ? s ingle conver s ion or timer-triggered mode ? interr u pt on conver s ion complete the at 8 9lp3240/6440 fe a t u re s a 10- b it su cce ss ive a pproxim a tion d a t a converter th a t f u nction s in either an a log-to-digit a l (adc) or digit a l-to-an a log (dac) mode. a b lock di a gr a m of the con- verter i s s hown in fig u re 20-1 . an 8 -ch a nnel an a log m u ltiplexer connect s eight s ingle-ended or fo u r differenti a l volt a ge inp u t s from the pin s of port 0 to a sa mple- a nd-hold circ u it th a t in t u rn provide s a n inp u t to the su cce ss ive a pproxim a tion b lock. the sa mple- a nd-hold circ u it en su re s th a t the inp u t volt a ge to the adc i s held a t a con s t a nt level d u ring conver s ion. the s ar b lock digitize s the a n a log volt a ge into a 10- b it v a l u e a cce ss i b le thro u gh a d a t a regi s ter. the s ar b lock a l s o oper a te s in rever s e to gener a te a n a n a log volt a ge on port 2 from a 10- b it digit a l v a l u e. adc re su lt s a re a v a il ab le in the dadl a nd dadh regi s ter p a ir. the adc re su lt s c a le i s deter- mined b y the reference volt a ge (v ref ) gener a ted either intern a lly from a 1.0v reference or extern a lly from v dd /2. the adc re su lt s a re a lw a y s repre s ented in s igned 2? s complement form, with s ingle-ended volt a ge ch a nnel s referring to the level ab ove or b elow v dd /2. the 10- b it re su lt s m a y b e right or left a dj us ted within the 16- b it regi s ter. the s ign i s extended thro u gh the 6 m s b s of right- a dj us ted re su lt s a nd the 6 l s b s of left- a dj us ted re su lt s a re zeroed. if only 8 - b it preci s ion i s req u ired, the us er s ho u ld s elect left- a dj us ted b y s etting ladj in dadc a nd re a d only the dadh regi s ter. ex a mple re su lt s a re li s ted in t ab le 20-1 . the conver s ion form u l as a re as follow s : conver s ion re su lt s c a n b e converted into u n s igned b in a ry b y a dding 02h to dadh in right- a dj us ted mode or 8 0h to dadh in left- a dj us ted mode. when us ing the extern a l reference (v dd /2) in s ingle-ended mode thi s i s eq u iv a lent to: to convert the u n s igned b in a ry v a l u e ba ck to 2? s complement, sub tr a ct 02h from dadh in right- a dj us ted mode or 8 0h from dadh in left- a dj us ted mode. note th a t the dadh/dadl regi s ter s c a nnot b e directly m a nip u l a ted as they a re re a d-only in adc mode a nd write-only in dac mode. ( s ingled-ended) adc 511 v in v dd 2 ? ? v ref ------------------------------------ = (differenti a l) adc 511 v in+ v in- ? v ref ---------------------------- = (un s igned s ingled-ended) adc 1023 v in v dd ---------- - =
134 3706c?micro?2/11 at89lp3240/6440 figure 20-1. dadc block di a gr a m table 20-1. ex a mple adc conver s ion code s right adjust left adjust single-ended mode (v in ) differential mode (v in + ? v in -) 00 v dd /2 0 0100h 4000h v dd /2 + 1/2 x v ref 1/2 x v ref 01ffh 7fc0h v dd /2 + 511/512 x v ref 511/512 x v ref ff00h c000h v dd /2 ? 1/2 x v ref ?1/2 x v ref fe01h 8 040h v dd /2 ? 511/512 x v ref ?511/512 x v ref 8-bit data bus 15 0 adc input select register (dadi) adc ctrl & status register (dadc) adc data register (dadh/dadl) acs2 dac adif acs1 acs0 ack0 ack1 ack2 diff 10-bit sar sample & hold internal 1.0v reference acon vdd adc7 adc6 adc5 adc4 adc 3 adc2 adc1 adc0 iref + - channel selection prescaler gnd pos. input mux neg. input mux trigger select timer overflows interrupt flag start avdd/2 da+ da- trg1 trg0 go adce ladj vref vin+ vin- r r vdd/2
135 3706c?micro?2/11 at89lp3240/6440 20.1 adc operation the adc convert s a n a n a log inp u t volt a ge to a 10- b it s igned digit a l v a l u e thro u gh su cce ss ive a pproxim a tion. when diff (dadi.3) i s zero, the adc oper a te s in s ingle-ended mode a nd the inp u t volt a ge i s the difference b etween the volt a ge a t the inp u t pin a nd v dd /2. in differenti a l mode (diff = 1) the inp u t volt a ge i s the difference b etween the po s itive a nd neg a tive inp u t pin s . the minim u m v a l u e repre s ent s zero difference a nd the m a xim u m v a l u e s repre s ent a difference of po s itive or neg a tive v ref min us 1 l s b. the a n a log inp u t ch a nnel i s s elected b y writing to the ac s b it s in dadi. any of the eight port 0 inp u t pin s c a n b e s elected as s ingle-ended inp u t s to the adc. fo u r p a ir s of port 0 pin s c a n b e s elected as differenti a l inp u t s . the acon b it (dadi.7) m us t b e s et to one to connect the inp u t pin s to the adc. prior to ch a nging ac s , acon m us t b e cle a red to zero. thi s en su re s th a t cro ss t a lk b etween ch a nnel s i s limited. acon m us t b e s et ba ck to one a fter ac s i s u pd a ted. acon a nd ac s s ho u ld not b e ch a nged while a conver s ion i s in progre ss . adc inp u t ch a nnel s m us t h a ve their port pin s config u red for inp u t-only mode. the adc i s en ab led b y s etting the adce b it in dadc. s ome s ettling time i s req u ired for the ref- erence circ u it s to s t ab ilize a fter the adc i s en ab led. the adc doe s not con su me power when adce i s cle a red, s o it i s recommended to s witch off the adc b efore entering power sa ving mode s . a timing di a gr a m of a n adc conver s ion i s s hown in fig u re 20-2 . the conver s ion req u ire s 13 adc clock cycle s to complete. the a n a log inp u t i s sa mpled d u ring the third cycle of the conver- s ion a nd i s held con s t a nt for the rem a inder of the conver s ion. at the end of the conver s ion, the interr u pt fl a g, adif, i s s et a nd the re su lt i s written to the d a t a regi s ter s . an a ddition a l 1 adc clock cycle a nd u p to 2 s y s tem clock cycle s m a y b e req u ired to s ynchronize adif with the re s t of the s y s tem. the re su lt s in dadh/dadl rem a in v a lid u ntil the next conver s ion complete s . dadh a nd dadl a re re a d-only regi s ter s d u ring adc mode. figure 20-2. adc timing di a gr a m the eq u iv a lent model for the a n a log inp u t circ u itry i s ill us tr a ted in fig u re 20-3 . an a n a log s o u rce a pplied to adcn i s sub jected to the pin c a p a cit a nce a nd inp u t le a k a ge of th a t pin, reg a rdle ss of whether th a t ch a nnel i s s elected as inp u t to the adc. when the ch a nnel i s s elected, the s o u rce m us t drive the s /h c a p a citor thro u gh the s erie s re s i s t a nce (com b ined re s i s t a nce in the inp u t p a th). to a chieve 10- b it re s ol u tion the s /h c a p a citor m us t b e ch a rged to within 1/2 l s b of the expected v a l u e within the 1 adc clock period sa mple time. high imped a nce s o u rce s m a y req u ire a red u ction in the adc clock freq u ency to a chieve f u ll re s ol u tion. 12 3 4 5 6 7 8 9 1011121 3 msb of result lsb of result adc clock go/bsy adif dadh dadl cycle number 12 one conversion next conversion 3 sample & hold initialize circuitry conversion complete initialize
136 3706c?micro?2/11 at89lp3240/6440 figure 20-3. eq u iv a lent an a log inp u t model 20.2 dac operation the dac convert s a 10- b it s igned digit a l v a l u e to a n a n a log o u tp u t c u rrent thro u gh su cce ss ive a pproxim a tion. the dac a lw a y s oper a te s in differenti a l mode, o u tp u tting a differenti a l c u rrent b etween it s po s itive (p2.2) a nd neg a tive (p2.3) o u tp u t s with a common mode volt a ge of v dd /2. the minim u m v a l u e repre s ent s zero difference a nd the m a xim u m v a l u e s repre s ent a difference of po s itive or neg a tive v ref min us 1 l s b. an extern a l tr a n s imped a nce a mplifier i s req u ired to convert the c u rrent into a volt a ge su it ab le for driving other circ u it s . the dac i s en ab led b y s etting the adce a nd dac b it s in dadc. s ome s ettling time i s req u ired for the reference circ u it s to s t ab ilize a fter the dac i s en ab led. the dac doe s not h a ve m u ltiple o u tp u t ch a nnel s a nd the diff, acon a nd ac s b it s h a ve no effect in dac mode. p2.2 a nd p2.3 a re au tom a tic a lly forced to inp u t-only mode while the dac i s en ab led. a timing di a gr a m of a dac conver s ion i s s hown in fig u re 20-4 . the conver s ion req u ire s 11 adc clock cycle s to complete. con s tr u ction of the a n a log o u tp u t s t a rt s in the s econd cycle of the con- ver s ion a nd the dac will a llow the new v a l u e to prop a g a te to the o u tp u t s d u ring cycle 7, a fter the 5 m s b s a re complete. at the end of the conver s ion, the interr u pt fl a g i s s et. an a ddition a l 1 adc clock cycle a nd u p to 2 s y s tem clock cycle s m a y b e req u ired to s ynchronize adif with the re s t of the s y s tem. the dadl a nd dadh regi s ter s hold the v a l u e to b e o u tp u t a nd a re write-only d u ring dac mode. an intern a l bu ffer sa mple s dadh/dadl a t the s t a rt of the conver s ion a nd hold s the v a l u e con s t a nt for the rem a inder of the conver s ion. one s y s tem clock cycle i s req u ired to tr a n s - fer the content s of dadh/dadl into the bu ffer a t the s t a rt of the conver s ion a nd therefore the adc clock freq u ency m us t a lw a y s b e eq ua l to or le ss th a n the s y s tem clock freq u ency d u ring dac mode to en su re th a t the bu ffer i s u pd a ted b efore the s econd cycle. figure 20-4. dac timing di a gr a m the eq u iv a lent model for the a n a log o u tp u t circ u itry i s ill us tr a ted in fig u re 20-5 . the s erie s o u t- p u t re s i s t a nce of the dac m us t drive the pin c a p a cit a nce a nd a ny extern a l lo a d on the pin. adcn c s/h = 2 pf r in = 10 k c pin = 10 pf r mux = 10 k 12 3 4567891011 msb of output lsb of output adc clock go/bsy adif dadh dadl cycle number 12 one conversion next conversion 3 begin output initialize circuitry conversion complete initialize
137 3706c?micro?2/11 at89lp3240/6440 figure 20-5. eq u iv a lent an a log o u tp u t model 20.3 clock selection the dadc req u ire s a clock of 2 mhz or le ss to a chieve f u ll re s ol u tion. by def au lt the dadc will us e a n intern a l 2 mhz clock gener a ted from the 8 mhz intern a l o s cill a tor. the intern a l o s cill a tor will b e en ab led even if it i s not su pplying the s y s tem clock. thi s m a y re su lt in higher power con- su mption. conver s ely, the dadc clock c a n b e gener a ted directly from the s y s tem clock us ing a 7- b it pre s c a ler. the pre s c a ler o u tp u t i s controlled b y the ack b it s in dadc as s hown in fig u re 20-6 . in adc mode, there a re no req u irement s on the clock freq u ency with re s pect to the s y s tem clock. the adc pre s c a ler s election i s independent of the s y s tem clock divider a nd the adc m a y oper a te a t b oth higher or lower freq u encie s th a n the cpu. however, in dac mode the adc clock freq u ency m us t not b e higher th a n the cpu clock, incl u ding a ny clock divi s ion from the s y s tem clock. figure 20-6. dadc clock s election 20.4 starting a conversion s etting the go/b s y b it (dadc.6) when adce = 1 s t a rt s a s ingle conver s ion in b oth adc a nd dac mode s . the b it rem a in s s et while the conver s ion i s in progre ss a nd i s cle a red b y h a rdw a re when the conver s ion complete s . the adc ch a nnel s ho u ld not b e ch a nged while a conver s ion i s in progre ss . altern a tively, a conver s ion c a n b e s t a rted au tom a tic a lly b y v a rio us timer s o u rce s . conver s ion trigger s o u rce s a re s elected b y the trg b it s in dadi. a conver s ion i s s t a rted every time the s elected timer overflow s , a llowing for conver s ion s to occ u r a t fixed interv a l s . the go/b s y b it will dan v out r out = 100 k c pin = 10 pf av dd /2 7-bit adc pre s caler adc clock s ource ck ack0 ack1 ack2 ck/12 8 ck/2 ck/4 ck/ 8 ck/16 ck/32 ck/64 internal 8 mhz o s c 4
138 3706c?micro?2/11 at89lp3240/6440 b e s et b y h a rdw a re while the conver s ion i s in progre ss . note th a t the timer overflow r a te m us t b e s lower th a n the conver s ion time. 20.5 noise considerations digit a l circ u itry in s ide a nd o u t s ide the device gener a te s emi which might a ffect the a cc u r a cy of a n a log me asu rement s . if conver s ion a cc u r a cy i s critic a l, the noi s e level c a n b e red u ced b y a pplying the following techniq u e s : ? connect a deco u pling c a p a citor b etween the v dd pin a nd gnd as s hown in fig u re 20-7 . thi s c a p a citor s ho u ld b e loc a ted as clo s e to the p a ck a ge as po ss i b le. ? keep a n a log s ign a l p a th s as s hort as po ss i b le. m a ke su re to r u n a n a log s ign a l s tr a ck s over a n a n a log gro u nd pl a ne, a nd keep them well a w a y from high- s peed digit a l tr a ck s . ?pl a ce the cpu in idle d u ring a conver s ion. ?if a ny port 0 pin s a re us ed as digit a l o u tp u t s , it i s e ss enti a l th a t the s e do not s witch while a conver s ion i s in progre ss . figure 20-7. ex a mple adc power connection s (tqfp p a ck a ge) analog ground plane p0.7 (adc7) 3 4 3 5 3 6 3 7 3 8 3 9 33 3 2 3 1 3 0 29 28 p0.6 (adc6) p0.5 (adc5) p0.4 (adc4) p0. 3 (adc 3 ) p0.2 (adc2) p0.1 (adc1) p0.0 (adc0) vdd vdd gnd 100 nf
139 3706c?micro?2/11 at89lp3240/6440 table 20-2. dadc ? dadc control regi s ter dadc = d9h re s et v a l u e = 0000 0000b not bit addre ssab le adif go/b s y dac adce ladj ack2 ack1 ack0 bit76543210 symbol function adif adc interr u pt fl a g. s et b y h a rdw a re when a conver s ion complete s . cle a red b y h a rdw a re when c a lling the interr u pt s ervice ro u tine. go/b s yconver s ion s t a rt/b us y fl a g. in s oftw a re triggered mode, writing a 1 to thi s b it s t a rt s a conver s ion. the b it rem a in s high while the conver s ion i s in progre ss a nd i s cle a red b y h a rdw a re when the conver s ion complete s . in h a rdw a re triggered mode, thi s b it i s s et a nd cle a red b y h a rdw a re to fl a g when the dadc i s bus y. dac digit a l-to-an a log conver s ion en ab le. s et to config u re the dadc in digit a l-to-an a log (dac) mode. cle a r to config u re the dadc in an a log-to-digit a l (adc) mode. adce dadc en ab le. s et to en ab le the dadc. cle a r to di sab le the dadc. ladj left adj us t en ab le. when cle a red, the adc re su lt s a re right a dj us ted a nd the m s b s a re s ign extended. when s et, the adc re su lt s a re left a dj us ted a nd the l s b s a re zeroed. ack [2-0] dadc clock s elect ack3 ack1 ack0 clock source 000intern a l rc o s cill a tor/4 (2mhz) 001f s y s /2 010f s y s /4 011f s y s / 8 100f s y s /16 101f s y s /32 110f s y s /64 111f s y s /12 8 table 20-3. dadl ? dadc d a t a low regi s ter dadl = dch re s et v a l u e = 0000 0000b not bit addre ssab le adc.7 adc.6 adc.5 adc.4 adc.3 adc.2 adc.1 adc.0 bit76543210 table 20-4. dadh ? dadc d a t a high regi s ter dadh = ddh re s et v a l u e = 0000 0000b not bit addre ssab le adc.15 adc.14 adc.13 adc.12 adc.11 adc.10 adc.9 adc. 8 bit76543210
140 3706c?micro?2/11 at89lp3240/6440 table 20-5. dadi ? dadc inp u t control regi s ter dadi = dah re s et v a l u e = 0000 0000b not bit addre ssab le acon iref trg1 trg0 diff ac s 2ac s 1ac s 0 bit76543210 symbol function acon an a log inp u t connect. when cle a red, the a n a log inp u t s a re di s connected from the adc. when s et, the a n a log inp u t s s elected b y ac s 2-0 a re connected to the adc. acon m us t b e zero when ch a nging the inp u t ch a nnel m u ltiplexor (ac s 2- 0 ). iref intern a l reference en ab le. when s et, the dadc us e s the intern a l volt a ge reference. when cle a red the dadc us e s vdd for it s reference. diff differenti a l mode en ab le. s et to config u re the adc in differenti a l mode. cle a r to config u re the adc in s ingle-ended mode. trg[1-0] trigger s elect. trg1 trg0 trigger 00 s oftw a re (go b it) 0 1 timer 0 overflow 1 0 timer 1 overflow 1 1 timer 2 overflow ac s [2-0] dadc ch a nnel s elect diff acs2 acs1 acs0 v+ v- 0000p0.0vdd/2 0001p0.1vdd/2 0010p0.2vdd/2 0011p0.3vdd/2 0100p0.4vdd/2 0101p0.5vdd/2 0110p0.6vdd/2 0111p0.7vdd/2 1000p0.0p0.1 1001p0.2p0.3 1010p0.4p0.5 1011p0.6p0.7 1100re s erved 1101re s erved 1110re s erved 1111re s erved
141 3706c?micro?2/11 at89lp3240/6440 21. programmable watchdog timer the progr a mm ab le w a tchdog timer (wdt) protect s the s y s tem from incorrect exec u tion b y trig- gering a s y s tem re s et when it time s o u t a fter the s oftw a re h as f a iled to feed the timer prior to the timer overflow. by def au lt the wdt co u nt s cpu clock cycle s . the pre s c a ler b it s , p s 0, p s 1 a nd p s 2 in s fr wdtcon a re us ed to s et the period of the w a tchdog timer from 16k to 204 8 k clock cycle s . the timer pre s c a ler c a n a l s o b e us ed to lengthen the time-o u t period ( s ee t ab le 6-2 on p a ge 33 ) the wdt i s di sab led b y re s et a nd d u ring power-down mode. when the wdt time s o u t witho u t b eing s erviced, a n intern a l r s t p u l s e i s gener a ted to re s et the cpu. s ee t ab le 21-1 for the a v a il ab le wdt period s election s . note: 1. the wdt time-o u t period i s dependent on the s y s tem clock freq u ency. the w a tchdog timer con s i s t s of a 14- b it timer with 7- b it progr a mm ab le pre s c a ler. writing the s eq u ence 1eh/e1h to the wdtr s t regi s ter en ab le s the timer. when the wdt i s en ab led, the wdten b it in wdtcon will b e s et to ?1?. to prevent the wdt from gener a ting a re s et when if overflow s , the w a tchdog feed s eq u ence m us t b e written to wdtr s t b efore the end of the time- o u t period. to feed the w a tchdog, two write in s tr u ction s m us t b e s eq u enti a lly exec u ted su cce ss - f u lly. between the two write in s tr u ction s , s fr re a d s a re a llowed, bu t write s a re not a llowed. the in s tr u ction s s ho u ld move 1eh to the wdtr s t regi s ter a nd then 1eh to the wdtr s t regi s ter. an incorrect feed or en ab le s eq u ence will c aus e a n immedi a te w a tchdog re s et. the progr a m s eq u ence to feed or en ab le the w a tchdog timer i s as follow s : mov wdtr s t, #01eh mov wdtr s t, #0e1h table 21-1. w a tchdog timer time-o u t period s election wdt prescaler bits period (1) (clock cycles) ps2 ps1 ps0 000 16k 001 32k 010 64k 011 12 8 k 100 256k 101 512k 1 1 0 1024k 111 204 8 k time-o u t period 2 ps 14 + () o s cill a tor freq u ency ------------------------------------------------------ - tps 1 + () =
142 3706c?micro?2/11 at89lp3240/6440 21.1 software reset a s oftw a re re s et of the at 8 9lp3240/6440 i s a ccompli s hed b y writing the s oftw a re re s et s eq u ence 5ah/a5h to the wdtr s t s fr. the wdt doe s not need to b e en ab led to gener a te the s oftw a re re s et. a norm a l s oftw a re re s et will s et the s wr s t fl a g in wdtcon. however, if a t a ny time a n incorrect s eq u ence i s written to wdtr s t (i.e. a nything other th a n 1eh/e1h or 5ah/a5h), a s oftw a re re s et will immedi a tely b e gener a ted a nd b oth the s wr s t a nd wdtovf fl a g s will b e s et. in thi s m a nner a n intention a l s oftw a re re s et m a y b e di s ting u i s hed from a s oft- w a re error-gener a ted re s et. the progr a m s eq u ence to gener a te a s oftw a re re s et i s as follow s : mov wdtr s t, #05ah mov wdtr s t, #0a5h table 21-2. wdtcon ? w a tchdog control regi s ter wdtcon addre ss = a7h re s et v a l u e = 0000 x000b not bit addre ssab le p s 2p s 1p s 0 wdidle ? s wr s t wdtovf wdten bit76543210 symbol function p s 2 p s 1 p s 0 pre s c a ler b it s for the w a tchdog timer (wdt). when a ll three b it s a re cle a red to 0, the w a tchdog timer h as a nomin a l period of 16k clock cycle s . when a ll three b it s a re s et to 1, the nomin a l period i s 204 8 k clock cycle s . wdidle di sab le/en ab le the w a tchdog timer in idle mode. when wdidle = 0, wdt contin u e s to co u nt in idle mode. when wdidle = 1, wdt freeze s while the device i s in idle mode. s wr s t s oftw a re re s et fl a g. s et when a s oftw a re re s et i s gener a ted b y writing the s eq u ence 5ah/a5h to wdtr s t. a l s o s et when a n incorrect s eq u ence i s written to wdtr s t. m us t b e cle a red b y s oftw a re. wdtovf w a tchdog overflow fl a g. s et when a wdt re s t i s gener a ted b y the wdt timer overflow. al s o s et when a n incorrect s eq u ence i s written to wdtr s t. m us t b e cle a red b y s oftw a re. wdten w a tchdog en ab le fl a g. thi s b it i s read-only a nd reflect s the s t a t us of the wdt (whether it i s r u nning or not). the wdt i s di sab led a fter a ny re s et a nd m us t b e re-en ab led b y writing 1eh/e1h to wdtr s t table 21-3. wdtr s t ? w a tchdog re s et regi s ter wdtcon addre ss = a6h (write-only) not bit addre ssab le ???????? bit76543210 the wdt i s en ab led b y writing the s eq u ence 1eh/e1h to the wdtr s t s fr. the c u rrent s t a t us m a y b e checked b y re a ding the wdten b it in wdtcon. to prevent the wdt from re s etting the device, the sa me s eq u ence 1eh/e1h m us t b e written to wdtr s t b efore the time-o u t interv a l expire s . a s oftw a re re s et i s gener a ted b y writing the s eq u ence 5ah/a5h to wdtr s t.
143 3706c?micro?2/11 at89lp3240/6440 22. instruction set summary the at 8 9lp3240/6440 i s f u lly b in a ry comp a ti b le with the 8 051 in s tr u ction s et. the difference b etween the at 8 9lp3240/6440 a nd the s t a nd a rd 8 051 i s the n u m b er of cycle s req u ired to exe- c u te a n in s tr u ction. in s tr u ction s in the at 8 9lp3240/6440 m a y t a ke 1 to 9 clock cycle s to complete. the exec u tion time s of mo s t in s tr u ction s m a y b e comp u ted us ing t ab le 22-1 . table 22-1. in s tr u ction exec u tion time s a nd exception s generic instruction types cycle count formula mo s t a rithmetic, logic a l, b it a nd tr a n s fer in s tr u ction s # b yte s br a nche s a nd c a ll s # b yte s + 1 s ingle byte indirect (i.e. add a, @ri, etc.) 2 ret, reti 4/5 (4) movc 3 movx 2/4 (2) mul 2 div 4 mac 9 inc dptr 2 arithmetic bytes clock cycles hex code 8051 at89lp add a, rn 1 12 1 2 8 -2f add a, direct 2 12 2 25 add a, @ri 1 12 2 26-27 add a, #d a t a 212 2 24 addc a, rn 1 12 1 3 8 -3f addc a, direct 2 12 2 35 addc a, @ri 1 12 2 36-37 addc a, #d a t a 212 2 34 s ubb a, rn 1 12 1 9 8 -9f s ubb a, direct 2 12 2 95 s ubb a, @ri 1 12 2 96-97 s ubb a, #d a t a 212 2 94 inc rn 1 12 1 0 8 -0f inc direct 2 12 2 05 inc @ri 1 12 2 06-07 inc a 2 12 2 04 dec rn 1 12 1 1 8 -1f dec direct 2 12 2 15 dec @ri 1 12 2 16-17 dec a 2 12 2 14 inc dptr 1 24 2 a3
144 3706c?micro?2/11 at89lp3240/6440 inc /dptr (1) 2? 3a5 a3 mul ab 1 4 8 2a4 div ab 1 4 8 4 8 4 da a 1 12 1 d4 mac ab (1) 2? 9a5 a4 clr m (1) 2? 2a5 e4 a s r m (1) 2? 2a5 03 l s l m (1) 2? 2a5 23 bit operations bytes clock cycles hex code 8051 at89lp clr c 1 12 1 c3 clr b it 2 12 2 c2 s etb c 1 12 1 d3 s etb b it 2 12 2 d2 cpl c 1 12 1 b3 cpl b it 2 12 2 b2 anl c, b it 2 24 2 8 2 anl c, b it 2 24 2 b0 orl c, b it 2 24 2 72 orl c, / b it 2 24 2 a0 mov c, b it 2 12 2 a2 mov b it, c 2 24 2 92 logical bytes clock cycles hex code 8051 at89lp clr a 1 12 1 e4 cpl a 1 12 1 f4 anl a, rn 1 12 1 5 8 -5f anl a, direct 2 12 2 55 anl a, @ri 1 12 2 56-57 anl a, #d a t a 212 2 54 anl direct, a 2 12 2 52 anl direct, #d a t a 324 3 53 orl a, rn 1 12 1 4 8 -4f orl a, direct 2 12 2 45 orl a, @ri 1 12 2 46-47 orl a, #d a t a 212 2 44 orl direct, a 2 12 2 42 orl direct, #d a t a 324 3 43 xrl a, rn 1 12 1 6 8 -6f table 22-1. in s tr u ction exec u tion time s a nd exception s (contin u ed)
145 3706c?micro?2/11 at89lp3240/6440 xrl a, direct 2 12 2 65 xrl a, @ri 1 12 2 66-67 xrl a, #d a t a 212 2 64 xrl direct, a 2 12 2 62 xrl direct, #d a t a 324 3 63 rl a 1 12 1 23 rlc a 1 12 1 33 rr a 1 12 1 03 rrc a 1 12 1 13 s wap a 1 12 1 c4 data transfer bytes clock cycles hex code 8051 at89lp mov a, rn 1 12 1 e 8 -ef mov a, direct 2 12 2 e5 mov a, @ri 1 12 2 e6-e7 mov a, #d a t a 212 2 74 mov rn, a 1 12 1 f 8 -ff mov rn, direct 2 24 2 a 8 -af mov rn, #d a t a 212 2 7 8 -7f mov direct, a 2 12 2 f5 mov direct, rn 2 24 2 88 - 8 f mov direct, direct 3 24 3 8 5 mov direct, @ri 2 24 2 8 6- 8 7 mov direct, #d a t a 324 3 75 mov @ri, a 1 12 1 f6-f7 mov @ri, direct 2 24 2 a6-a7 mov @ri, #d a t a 2 12 2 76-77 mov dptr, #d a t a 16 3 24 3 90 mov /dptr, #d a t a 16 (1) 4? 4a5 90 movc a, @a+dptr 1 24 3 93 movc a, @a+/dptr (1) 2? 4a5 93 movc a, @a+pc 1 24 3 8 3 movx a, @ri 1 24 2 e2-e3 movx a, @dptr 1 24 2/4 (2) e0 movx a, @/dptr (1) 2?3/5 (2) a5 e0 movx @ri, a 1 24 2 f2-f3 movx @dptr, a 1 24 2/4 (2) f0 movx @/dptr, a (1) 2?3/5 (2) a5 f0 pu s h direct 2 24 2/3 (4) c0 table 22-1. in s tr u ction exec u tion time s a nd exception s (contin u ed)
146 3706c?micro?2/11 at89lp3240/6440 note s :1.thi s e s c a ped in s tr u ction i s a n exten s ion to the in s tr u ction s et. s ee s ection 22.1 on p a ge 147 . 2. movx @dptr in s tr u ction s t a ke 2 clock cycle s when a cce ss ing eram a nd 4 clock cycle s when a cce ss ing fdata, xdata or code. (3 a nd 5 cycle s for movx @/dptr). 3. the break in s tr u ction a ct s as a 2 cycle nop. 4. in s tr u ction s a cce ss ing the s t a ck req u ire a ddition a l cycle s when us ing the extended s t a ck. pop direct 2 24 2/3 (4) d0 xch a, rn 1 12 1 c 8 -cf xch a, direct 2 12 2 c5 xch a, @ri 1 12 2 c6-c7 xchd a, @ri 1 12 2 d6-d7 branching bytes clock cycles hex code 8051 at89lp jc rel 2 24 3 40 jnc rel 2 24 3 50 jb b it, rel 3 24 4 20 jnb b it, rel 3 24 4 30 jbc b it, rel 3 24 4 10 jz rel 2 24 3 60 jnz rel 2 24 3 70 s jmp rel 2 24 3 8 0 acall a ddr11 2 24 3/5 (4) 11,31,51,71,91, b1,d1,f1 lcall a ddr16 3 24 4/6 (4) 12 ret 1 24 4/5 (4) 22 reti 1 24 4/5 (4) 32 ajmp a ddr11 2 24 3 01,21,41,61, 8 1, a1,c1,e1 ljmp a ddr16 3 24 4 02 jmp @a+dptr 1 24 2 73 jmp @a+pc (1) 2? 3a573 cjne a, direct, rel 3 24 4 b5 cjne a, #d a t a , rel 3 24 4 b4 cjne rn, #d a t a , rel 3 24 4 b 8 -bf cjne @ri, #d a t a , rel 3 24 4 b6-b7 cjne a, @r0, rel (1) 3? 4a5 b6 cjne a, @r1, rel (1) 3? 4a5 b7 djnz rn, rel 2 24 3 d 8 -df djnz direct, rel 3 24 4 d5 nop 1 12 1 00 break (1)(3) 2? 2a500 table 22-1. in s tr u ction exec u tion time s a nd exception s (contin u ed)
147 3706c?micro?2/11 at89lp3240/6440 22.1 instruction set extensions the following in s tr u ction s a re exten s ion s to the s t a nd a rd 8 051 in s tr u ction s et th a t provide enh a nced c a p ab ilitie s not fo u nd in s t a nd a rd 8 051 device s . all extended in s tr u ction s s t a rt with a n a5h e s c a pe code. for thi s re as on r a ndom a5h re s erved code s s ho u ld not b e pl a ced in the in s tr u ction s tre a m even tho u gh other device s m a y h a ve tre a ted the s e as nop s . other at 8 9lp device s m a y not su pport a ll of the s e in s tr u ction s . 22.1.1 asr m function: s hift mac acc u m u l a tor right arithmetic a lly description: the forty b it s in the m regi s ter a re s hifted one b it to the right. bit 39 ret a in s it s v a l u e to pre s erve the s ign of the v a l u e. no fl a g s a re a ffected. example: the m regi s ter hold s the v a l u e 0c5b1a293 8 4h . the following in s tr u ction, a s r m le a ve s the m regi s ter holding the v a l u e 0e2d 8 d149c2h. bytes: 2 cycles: 2 encoding: a5 00000011 operation: a s r (m n ) (m n + 1 ) n = 0 - 3 8 (m 39 ) (m 39 ) 22.1.2 break function: s oftw a re bre a kpoint (h a lt exec u tion) description: break tr a n s fer s control from norm a l exec u tion to the on-chip de bu g (ocd) h a ndler if ocd i s en ab led. the pc i s left pointing to the following in s tr u ction. if ocd i s di sab led, break a ct s as a do ub le nop. no fl a g s a re a ffected. example: if on-chip de bu gging i s a llowed, the following in s tr u ction, break will h a lt in s tr u ction exec u tion prior to the immedi a tely following in s tr u ction. if de bu gging i s not a llowed, the break i s tre a ted as a do ub le nop. bytes: 2 cycles: 2 encoding: a5 00000000 operation: break (pc) (pc) + 2
148 3706c?micro?2/11 at89lp3240/6440 22.1.3 cjne a, @r i , rel function: comp a re a nd j u mp if not eq ua l description: cjne comp a re s the m a gnit u de s of the acc u m u l a tor a nd indirect ram loc a tion a nd b r a nche s if their v a l u e s a re not eq ua l. the b r a nch de s tin a tion i s comp u ted b y a dding the s igned rel a tive-di s pl a cement in the l as t in s tr u ction b yte to the pc, a fter incrementing the pc to the s t a rt of the next in s tr u ction. the c a rry fl a g i s s et if the u n s igned integer v a l u e of acc i s le ss th a n the u n s igned integer v a l u e of the indirect loc a tion; otherwi s e, the c a rry i s cle a red. neither oper a nd i s a ffected. example: the acc u m u l a tor cont a in s 34h. regi s ter 0 cont a in s 7 8 h a nd 7 8 h cont a in s 56h. the fir s t in s tr u ction in the s eq u ence, cjne a, @r0, not_eq ; . . . . . . ...... ...... ; acc = @r0. not_eq: jc req_low .. ;if acc< @r0. ; . . . . . . ...... ...... ;acc > @r0. s et s the c a rry fl a g a nd b r a nche s to the in s tr u ction a t l ab el not_eq. by te s ting the c a rry fl a g, the s econd in s tr u ction determine s whether acc i s gre a ter or le ss th a n the loc a tion pointed to b y r0. bytes: 2 cycles: 9 encoding: a5 1011011 i rel. a ddre ss operation: cjne (pc) (pc) + 3 if (a) ((r i )) then (pc) (pc) + rel a tive off s et if (a) < ((r i )) then (c) 1 el s e (c) 0 22.1.4 clr m function: cle a r mac acc u m u l a tor description: clr m cle a r s the 40- b it m regi s ter. no fl a g s a re a ffected. example: the m regi s tercont a in s 1234567 8 9ah. the following in s tr u ction, clr m le a ve s the m regi s ter s et to 0000000000h. bytes: 2 cycles: 2 encoding: a5 11100100 operation: jmp (m) 0
149 3706c?micro?2/11 at89lp3240/6440 22.1.5 inc /dptr function: increment altern a te d a t a pointer description: inc /dptr increment s the u n s elected 16- b it d a t a pointer b y 1. a 16- b it increment (mod u lo 2 16 ) i s performed, a nd a n overflow of the low-order b yte of the d a t a pointer from 0ffh to 00h increment s the high-order b yte. no fl a g s a re a ffected. example: regi s ter s dp1h a nd dp1l cont a in 12h a nd 0feh, re s pectively, a nd dp s = 0. the following in s tr u ction s eq u ence, inc /dptr inc /dptr inc /dptr ch a nge s dp1h a nd dp1l to 13h a nd 01h. bytes: 2 cycles: 3 encoding: a5 10100011 operation: inc if (dp s ) = 0 then (dptr1) (dptr1) + 1 el s e (dptr0) (dptr0) + 1 22.1.6 jmp @a+pc function: j u mp indirect rel a tive to pc description: jmp @a+pc a dd s the eight- b it u n s igned content s of the acc u m u l a tor to the progr a m co u nter, which i s fir s t incremented b y two. thi s i s the a ddre ss for subs eq u ent in s tr u ction fetche s . s ixteen- b it a ddition i s performed (mod u lo 2 16 ): a c a rry-o u t from the low-order eight b it s prop a g a te s thro u gh the higher-order b it s . the acc u m u l a tor i s not a ltered. no fl a g s a re a ffected. example: an even n u m b er from 0 to 6 i s in the acc u m u l a tor. the following s eq u ence of in s tr u ction s b r a nche s to one of fo u r ajmp in s tr u ction s in a j u mp t ab le s t a rting a t jmp_tbl. jmp @a + pc jmp_tbl: ajmp label0 ajmp label1 ajmp label2 ajmp label3 if the acc u m u l a tor eq ua l s 04h when s t a rting thi s s eq u ence, exec u tion j u mp s to l ab el label2. bec aus e ajmp i s a 2- b yte in s tr u ction, the j u mp in s tr u ction s s t a rt a t every other a ddre ss . bytes: 2 cycles: 3 encoding: a5 01110011 operation: jmp (pc) (a) + (pc) + 2
150 3706c?micro?2/11 at89lp3240/6440 22.1.7 lsl m function: s hift mac acc u m u l a tor left logic a lly description: the forty b it s in the m regi s ter a re s hifted one b it to the left. bit 0 i s cle a red. no fl a g s a re a ffected. example: the m regi s ter hold s the v a l u e 0c5b1a293 8 4h. the following in s tr u ction, l s l m le a ve s the m regi s ter holding the v a l u e 8 b6345270 8 h. bytes: 2 cycles: 2 encoding: a5 00100011 operation: l s l (m n+1 ) (m n ) n = 0 - 3 8 (m 0 ) 0 22.1.8 movc a, @a+/dptr function: move code b yte rel a tive to altern a te d a t a pointer description: the movc in s tr u ction s lo a d the acc u m u l a tor with a code b yte or con s t a nt from progr a m memory. the a ddre ss of the b yte fetched i s the su m of the origin a l u n s igned 8 - b it acc u m u l a tor content s a nd the content s of the u n s elected d a t a pointer. the bas e regi s ter i s not a ltered. s ixteen- b it a ddition i s performed s o a c a rry-o u t from the low-order eight b it s m a y prop a g a te thro u gh higher-order b it s . no fl a g s a re a ffected. example: a v a l u e b etween 0 a nd 3 i s in the acc u m u l a tor. the following in s tr u ction s will tr a n s l a te the v a l u e in the acc u m u l a tor to one of fo u r v a l u e s defined b y the db (define b yte) directive. mov /dptr, #table movc a, @a+pc ret table: db 66h db 77h db 88 h db 99h if the sub ro u tine i s c a lled with the acc u m u l a tor eq ua l to 01h, it ret u rn s with 77h in the acc u m u l a tor. bytes: 2 cycles: 4 encoding: a5 10010011 operation: movc if (dp s ) = 0 then (a) ( (a) + (dptr1) ) el s e (a) ( (a) + (dptr0) )
151 3706c?micro?2/11 at89lp3240/6440 22.1.9 mac ab function: m u ltiply a nd acc u m u l a te description: mac ab m u ltiplie s the s igned 16- b it integer s in the regi s ter p a ir s {ax, a} a nd {bx, b} a nd a dd s the 32- b it prod u ct to the 40- b it m regi s ter. the low-order b yte s of the 16- b it oper a nd s a re s tored in a a nd b, a nd the high-order b yte s in ax a nd bx re s pectively. the fo u r oper a nd regi s ter s a re u n a ffected b y the oper a tion. if the a ddition of the prod u ct to the a cc u m u l a ted su m in m re su lt s in a two' s complement overflow, the overflow fl a g i s s et; otherwi s e it i s not cle a red. the c a rry fl a g i s s et if the re su lt i s neg a tive a nd cle a red if po s itive. example: origin a lly the acc u m u l a tor hold s the v a l u e 8 0 (50h). regi s ter b hold s the v a l u e 160 (0a0h). the in s tr u ction, mac ab will give the prod u ct 12, 8 00 (3200h), s o b i s ch a nged to 32h (00110010b) a nd the acc u m u l a tor i s cle a red. the overflow fl a g i s s et, c a rry i s cle a red. bytes: 2 cycles: 9 encoding: a5 10100100 operation: mac (m 39-0 ) (m) + { (ax), (a) } x { (bx), (b) } 22.1.10 mov /dptr, #data16 function: lo a d altern a te d a t a pointer with a 16- b it con s t a nt description: mov /dptr, #d a t a 16 lo a d s the u n s elected d a t a pointer with the 16- b it con s t a nt indic a ted. the third b yte i s the high-order b yte, while the fo u rth b yte hold s the lower-order b yte. no fl a g s a re a ffected. example: when dp s = 0, the in s tr u ction s eq u ence, mov dptr, # 1234h mov /dptr, # 567 8 h lo a d s the v a l u e 1234h into the fir s t d a t a pointer: dph0 hold s 12h a nd dpl0 hold s 34h; a nd lo a d s the v a l u e 567 8 h into the s econd d a t a pointer: dph1 hold 56h a nd dpl1 hold s 7 8 h. bytes: 2 cycles: 3 encoding: a5 90 immed. d a t a 15- 8 immed. d a t a 7-0 operation: mov if (dp s ) = 0 then (dp1h) #d a t a 15- 8 (dp1l) #d a t a 7-0 el s e (dp0h) #d a t a 15- 8 (dp0l) #d a t a 7-0
152 3706c?micro?2/11 at89lp3240/6440 22.1.11 movx a, @/dptr function: move extern a l us ing altern a te d a t a pointer description: the movx in s tr u ction tr a n s fe s r d a t a from extern a l d a t a memory to the acc u m u l a tor. the u n s elected d a t a pointer gener a te s a 16- b it a ddre ss which t a rget s edata, fdata or xdata. example: dp s = 0, dptr0 cont a in s 0123h a nd dptr1 cont a in s 4567h. the following in s tr u ction s eq u ence, movx a, @dptr movx @/dptr, a copie s the d a t a from a ddre ss 0123h to 4567h. bytes: 2 cycles: 3 (edata) 5 (fdata or xdata) encoding: a5 11100000 operation: movx if (dp s ) = 0 (a) ((dptr1)) el s e (a) ((dptr0)) 22.1.12 movx @/dptr, a function: move extern a l us ing altern a te d a t a pointer description: the movx in s tr u ction tr a n s fe s r d a t a from the acc u m u l a tor to extern a l d a t a memory. the u n s elected d a t a pointer gener a te s a 16- b it a ddre ss which t a rget s edata, fdata or xdata. example: dp s = 0, dptr0 cont a in s 0123h a nd dptr1 cont a in s 4567h. the following in s tr u ction s eq u ence, movx a, @dptr movx @/dptr, a copie s the d a t a from a ddre ss 0123h to 4567h. bytes: 2 cycles: 3 (edata) 5 (fdata or xdata) encoding: a5 11110000 operation: movx if (dp s ) = 0 then ((dptr1)) (a) el s e ((dptr0)) (a)
153 3706c?micro?2/11 at89lp3240/6440 23. register index table 23-1. s peci a l f u nction regi s ter cro ss reference name address description index acc e0h ac s ra 97h t ab le 19-1 on p a ge 130 ac s rb 9fh t ab le 19-2 on p a ge 131 aref afh t ab le 19-3 on p a ge 132 auxr 8 eh t ab le 3-4 on p a ge 1 8 ax e1h s ection 5.1 on p a ge 24 bf0h bx f7h s ection 5.1 on p a ge 24 clkreg 8 fh t ab le 6-2 on p a ge 33 dadc d9h t ab le 20-2 on p a ge 139 dadh ddh t ab le 20-4 on p a ge 139 dadi dah t ab le 20-3 on p a ge 139 dadl dch t ab le 20-3 on p a ge 139 dpcf (auxr1) a2h t ab le 5-5 on p a ge 2 8 dph0 8 3h s ection 5.2 on p a ge 25 dph1 8 5h s ection 5.2 on p a ge 25 dpl0 8 2h s ection 5.2 on p a ge 25 dpl1 8 3h s ection 5.2 on p a ge 25 d s pr e2h t ab le 5-1 on p a ge 26 fird e3h s ection 5.2.2.3 on p a ge 29 gpien 9ch t ab le 15-3 on p a ge 8 4 gpif 9dh t ab le 15-4 on p a ge 8 4 gpl s 9bh t ab le 15-2 on p a ge 8 4 gpmod 9ah t ab le 15-1 on p a ge 8 4 ie a 8 h t ab le 9-2 on p a ge 42 ie2 b4h t ab le 9-3 on p a ge 43 ip b 8 h t ab le 9-4 on p a ge 43 ip2 b5h t ab le 9-5 on p a ge 43 iph b7h t ab le 9-6 on p a ge 44 iph2 b6h t ab le 9-7 on p a ge 44 mach e5h s ection 5.1 on p a ge 24 macl e4h s ection 5.1 on p a ge 24 memcon 96h t ab le 3-3 on p a ge 17 p0 8 0h t ab le 10-3 on p a ge 45 p0m0 bah t ab le 10-2 a nd t ab le 10-3 on p a ge 45 p0m1 bbh t ab le 10-2 a nd t ab le 10-3 on p a ge 45
154 3706c?micro?2/11 at89lp3240/6440 p1 90h t ab le 10-3 on p a ge 45 p1m0 c2h t ab le 10-2 a nd t ab le 10-3 on p a ge 45 p1m1 c3h t ab le 10-2 a nd t ab le 10-3 on p a ge 45 p2 a0h t ab le 10-3 on p a ge 45 p2m0 c4h t ab le 10-2 a nd t ab le 10-3 on p a ge 45 p2m1 c5h t ab le 10-2 a nd t ab le 10-3 on p a ge 45 p3 b0h t ab le 10-3 on p a ge 45 p3m0 c6h t ab le 10-2 a nd t ab le 10-3 on p a ge 45 p3m1 c7h t ab le 10-2 a nd t ab le 10-3 on p a ge 45 p4 c0h t ab le 10-3 on p a ge 45 p4m0 beh t ab le 10-2 a nd t ab le 10-3 on p a ge 45 p4m1 bfh t ab le 10-2 a nd t ab le 10-3 on p a ge 45 pag e 8 6h t ab le 3-2 on p a ge 14 pcon 8 7h t ab le 8 -1 on p a ge 37 p s wd0h rcap2h cbh s ection 12.1 on p a ge 61 rcap2l cah s ection 12.1 on p a ge 61 rh0 94h t ab le 11-1 on p a ge 51 rh1 95h t ab le 11-1 on p a ge 51 rl0 92h t ab le 11-1 on p a ge 51 rl1 93h t ab le 11-1 on p a ge 51 s addr a9h s ection 16.7 on p a ge 97 s aden b9h s ection 16.7 on p a ge 97 s buf 99h s ection 16.3 on p a ge 8 9 s con 9 8 h t ab le 16-1 on p a ge 8 6 s p 8 1h s ection 3.4 on p a ge 20 s pcr e9h t ab le 17-2 on p a ge 102 s pdr eah t ab le 17-3 on p a ge 103 s p s re 8 h t ab le 17-4 on p a ge 103 s px 9eh s ection 3.4 on p a ge 20 t2cca d1h t ab le 13-1 on p a ge 71 t2ccc d4h t ab le 13-5 on p a ge 74 t2ccf d5h t ab le 13-4 on p a ge 72 t2cch d3h t ab le 13-2 on p a ge 71 t2ccl d2h t ab le 13-3 on p a ge 71 t2con c 8 h t ab le 12-3 on p a ge 61 t2mod c9h t ab le 12-4 on p a ge 61 tcon 88 h t ab le 11-2 on p a ge 54 tconb 91h t ab le 11-4 on p a ge 56 table 23-1. s peci a l f u nction regi s ter cro ss reference
155 3706c?micro?2/11 at89lp3240/6440 24. on-chip debug system the at 8 9lp3240/6440 on-chip de bu g (ocd) s y s tem us e s a two-wire s eri a l interf a ce to con- trol progr a m flow; re a d, modify, a nd write the s y s tem s t a te; a nd progr a m the nonvol a tile memory. the ocd s y s tem h as the following fe a t u re s : ? complete progr a m flow control ?re a d-modify-write a cce ss to a ll intern a l s fr s a nd d a t a memorie s ?fo u r h a rdw a re progr a m a ddre ss b re a kpoint s , pl us fo u r progr a m/d a t a a ddre ss b re a kpoint s ? unlimited progr a m s oftw a re b re a kpoint s us ing break in s tr u ction ?bre a k on ch a nge in progr a m memory flow ?bre a k on s t a ck overflow/ u nderflow ?bre a k on w a tchdog overflow ?bre a k on re s et ? non-intr us ive oper a tion ?progr a mming of nonvol a tile memory 24.1 physical interface the on-chip de bu g s y s tem us e s a two-wire s ynchrono us s eri a l interf a ce to e s t ab li s h comm u ni- c a tion b etween the t a rget device a nd the controlling em u l a tor s y s tem. the ocd interf a ce i s en ab led b y cle a ring the ocd en ab le f us e. the ocd device connection s a re s hown in fig u re 24-1 . when ocd i s en ab led, the r s t port pin i s config u red as a n inp u t for the de bu g clock (dcl). either the xtal1, xtal2 or p4.3 pin i s config u red as a b i-direction a l d a t a line for the de bu g d a t a (dda) depending on the clock s o u rce s elected. if the intern a l rc o s cill a tor i s s elected, xtal1 i s config u red as dda (a).if the extern a l clock i s s elected, xtal2 i s config u red as dda (b). if the cry s t a l o s cill a tor i s s elected, p4.3 i s config u red as dda (c). when de s igning a s y s tem where on-chip de bu g will b e us ed, the following o bs erv a tion s m us t b e con s idered for correct oper a tion: th0 8 ch t ab le 11-1 on p a ge 51 th1 8 dh t ab le 11-1 on p a ge 51 th2 cdh s ection 12.1 on p a ge 61 tl0 8 ah t ab le 11-1 on p a ge 51 tl1 8 bh t ab le 11-1 on p a ge 51 tl2 cch s ection 12.1 on p a ge 61 tmod 8 9h t ab le 11-3 on p a ge 55 twar ach t ab le 1 8 -3 on p a ge 112 twbr aeh t ab le 1 8 -5 on p a ge 113 twcr aah t ab le 1 8 -1 on p a ge 112 twdr adh t ab le 1 8 -4 on p a ge 113 tw s r abh t ab le 1 8 -2 on p a ge 112 wdtcon a7h t ab le 21-2 on p a ge 142 wdtr s t a6h t ab le 21-3 on p a ge 142 table 23-1. s peci a l f u nction regi s ter cro ss reference
156 3706c?micro?2/11 at89lp3240/6440 ? p4.2/r s t c a nnot b e connected directly to v dd a nd a ny extern a l c a p a citor s connected to r s t m us t b e removed. ? all extern a l re s et s o u rce s m us t b e removed. ? if p4.3 need s to b e de bu gged in s y s tem s us ing the cry s t a l o s cill a tor, the extern a l clock option s ho u ld b e s elected. the q ua rtz cry s t a l a nd a ny c a p a citor s on xtal1 or xtal2 m us t b e removed a nd a n extern a l clock s ign a l m us t b e driven on xtal1. s ome em u l a tor s y s tem s m a y provide a us er-config u r ab le clock for thi s p u rpo s e. figure 24-1. at 8 9lp3240/6440 on-chip de bu g connection s 24.2 software breakpoints the at 8 9lp3240/6440 microcontroller incl u de s a break in s tr u ction for implementing progr a m memory b re a kpoint s in s oftw a re. a s oftw a re b re a kpoint c a n b e in s erted m a n ua lly b y pl a cing the break in s tr u ction in the progr a m code. s ome em u l a tor s y s tem s m a y a llow for au tom a tic in s er- tion/deletion of s oftw a re b re a kpoint s . the fl as h memory m us t b e re-progr a mmed e a ch time a s oftw a re b re a kpoint i s ch a nged. freq u ent in s ertion s /deletion s of s oftw a re b re a kpoint s will red u ce the end u r a nce of the nonvol a tile memory. device s us ed for de bu gging p u rpo s e s s ho u ld not b e s hipped to end c us tomer s . the break in s tr u ction i s tre a ted as a two-cycle nop when ocd i s di sab led. 24.3 limitations of on-chip debug the at 8 9lp3240/6440 i s a f u lly-fe a t u red microcontroller th a t m u ltiplexe s s ever a l f u nction s on it s limited i/o pin s . s ome device f u nction a lity m us t b e sa crificed to provide re s o u rce s for on- chip de bu gging. the on-chip de bu g s y s tem h as the following limit a tion s : ?the de bu g clock pin (dcl) i s phy s ic a lly loc a ted on th a t sa me pin as port pin p4.2 a nd the extern a l re s et (r s t ). therefore, neither p4.2 nor a n extern a l re s et s o u rce m a y b e em u l a ted when ocd i s en ab led. clk = intern a l rc vdd xtal1 p4.2/r s t gnd dcl dda clk = extern a l clock vdd xtal2 p4.2/r s t gnd dcl dda xtal1 clk clk = cry s t a l o s cill a tor vdd p4.3 p4.2/r s t gnd dcl dda xtal1 xtal2 ab c
157 3706c?micro?2/11 at89lp3240/6440 ? when us ing the intern a l rc o s cill a tor d u ring de bu g, dda i s loc a ted on the xtal1/p4.0 pin. the p4.0 i/o f u nction c a nnot b e em u l a ted in thi s mode. ? when us ing the extern a l clock d u ring de bu g, dda i s loc a ted on the xtal2/p4.1 pin a nd the s y s tem clock drive s xtal1/p4.0. the p4.1 i/o a nd clkout f u nction s c a nnot b e em u l a ted in thi s mode. ? when us ing the cry s t a l o s cill a tor d u ring de bu g, dda i s loc a ted on the p4.3 pin a nd the cry s t a l connect s to xtal1/p4.0 a nd xtal2/p4.1. the p4.3 i/o f u nction c a nnot b e em u l a ted in thi s mode. 25. programming the flash memory the atmel at 8 9lp3240/6440 microcontroller fe a t u re s 64k b yte s of on-chip in- s y s tem progr a m- m ab le fl as h progr a m memory a nd 8 k b yte s of nonvol a tile fl as h d a t a memory. in- s y s tem progr a mming a llow s progr a mming a nd reprogr a mming of the microcontroller po s itioned in s ide the end s y s tem. u s ing a s imple 4-wire s pi interf a ce, the progr a mmer comm u nic a te s s eri a lly with the at 8 9lp3240/6440 microcontroller, reprogr a mming a ll nonvol a tile memorie s on the chip. in- s y s tem progr a mming elimin a te s the need for phy s ic a l remov a l of the chip s from the s y s tem. thi s will sa ve time a nd money, b oth d u ring development in the l ab , a nd when u pd a ting the s oftw a re or p a r a meter s in the field. the progr a mming interf a ce of the at 8 9lp3240/6440 incl u de s the following fe a t u re s : ?fo u r-wire s eri a l s pi progr a mming interf a ce or 11-pin p a r a llel interf a ce ? active-low re s et entry into progr a mming ? s l a ve s elect a llow s m u ltiple device s on sa me interf a ce ?u s er s ign a t u re arr a y ?flexi b le p a ge progr a mming ?row er as e c a p ab ility ?p a ge write with a u to-er as e comm a nd s ?progr a mming s t a t us regi s ter for more det a iled inform a tion on in- s y s tem progr a mming, refer to the applic a tion note entitled ?at 8 9lp in- s y s tem progr a mming s pecific a tion?. 25.1 physical interface the at 8 9lp3240/6440 provide s a s t a nd a rd progr a mming comm a nd s et with two phy s ic a l inter- f a ce s : a b it- s eri a l a nd a b yte-p a r a llel interf a ce. norm a l fl as h progr a mming u tilize s the s eri a l peripher a l interf a ce ( s pi) pin s of a n at 8 9lp3240/6440 microcontroller. the s pi i s a f u ll-d u plex s ynchrono us s eri a l interf a ce con s i s ting of fo u r wire s : s eri a l clock ( s ck), m as ter-in/ s l a ve-o u t (mi s o), m as ter-o u t/ s l a ve-in (mo s i), a nd a n a ctive-low chip s elect a nd fr a me s ign a l ( ss ). when progr a mming a n at 8 9lp3240/6440 device, the progr a mmer a lw a y s oper a te s as the s pi m as - ter, a nd the t a rget s y s tem a lw a y s oper a te s as the s pi s l a ve. to enter or rem a in in progr a mming mode the device? s re s et line (r s t ) m us t b e held a ctive (low). with the a ddition of vdd a nd gnd, a n at 8 9lp3240/6440 microcontroller c a n b e progr a mmed with a minim u m of s even con- nection s as s hown in fig u re 25-1 . in a ddition to b eing a chip s elect, the ss pin a l s o i s us ed to fr a me a comm a nd p a cket. ss m us t go low b efore the s t a rt of a comm a nd a nd m us t ret u rn high to complete the comm a nd. ss must not be tied to ground as this will prevent the interface from recognizing mutiple com- mands . ss s ho u ld b e connected to the progr a mming m as ter for correct oper a tion.
158 3706c?micro?2/11 at89lp3240/6440 figure 25-1. in- s y s tem progr a mming device connection s the p a r a llel interf a ce i s a s peci a l mode of the s eri a l interf a ce, i.e. the s eri a l interf a ce i s us ed to en ab le the p a r a llel interf a ce. after en ab ling the interf a ce s eri a lly over p1.7/ s ck a nd p1.5/mo s i, p1.5 i s reconfig u red as a n a ctive-low o u tp u t en ab le (oe ) for d a t a on port 0. when oe =1, com- m a nd, a ddre ss a nd write d a t a b yte s a re inp u t on port 0 a nd sa mpled a t the ri s ing edge of s ck. when oe =0, re a d d a t a b yte s a re o u tp u t on port 0 a nd s ho u ld b e sa mpled on the f a lling edge of s ck. the p1.7/ s ck, p1.4/ ss a nd p4.2/r s t pin s contin u e to f u nction in the sa me m a nner. with the a ddition of vdd a nd gnd, the p a r a llel interf a ce req u ire s a minim u m of fo u rteen connection s as s hown in fig u re 25-2 . note th a t a connection to p1.6/mi s o i s not req u ired for us ing the p a r- a llel interf a ce. figure 25-2. p a r a llel progr a mming device connection s the progr a mming interf a ce i s the only me a n s of extern a lly progr a mming the at 8 9lp3240/6440 microcontroller. the interf a ce c a n b e us ed to progr a m the device b oth in- s y s tem a nd in a s t a nd- a lone s eri a l progr a mmer. the interf a ce doe s not req u ire a ny clock other th a n s ck a nd i s not limited b y the s y s tem clock freq u ency. d u ring progr a mming the s y s tem clock s o u rce of the t a r- get device c a n oper a te norm a lly. when de s igning a s y s tem where in- s y s tem progr a mming will b e us ed, the following o bs erv a - tion s m us t b e con s idered for correct oper a tion: at 8 9lp3240/6440 vdd p4.2/r s t p1.7/ s ck p1.5/mo s i gnd s eri a l clock s eri a l in r s t p1.4/ ss p1.6/mi s o s eri a l o u t ss at 8 9lp3240/6440 vdd p4.2/r s t p1.7/ s ck p1.5/mo s i gnd clock oe r s t p1.4/ ss ss p0.7-0 d a t a in/o u t 8
159 3706c?micro?2/11 at89lp3240/6440 ?the i s p interf a ce us e s the s pi clock mode 0 (cpol = 0, cpha = 0) excl us ively with a m a xim u m freq u ency of 5 mhz. ?the at 8 9lp3240/6440 will enter progr a mming mode only when it s re s et line (r s t ) i s a ctive (low). to s implify thi s oper a tion, it i s recommended th a t the t a rget re s et c a n b e controlled b y the in- s y s tem progr a mmer. to a void pro b lem s , the in- s y s tem progr a mmer s ho u ld b e ab le to keep the entire t a rget s y s tem re s et for the d u r a tion of the progr a mming cycle. the t a rget s y s tem s ho u ld never a ttempt to drive the fo u r s pi line s while re s et i s a ctive. ?the r s t inp u t m a y b e di sab led to g a in a n extr a i/o pin. in the s e c as e s the r s t pin will a lw a y s f u nction as a re s et d u ring power u p. to enter progr a mming the r s t pin m us t b e driven low prior to the end of power-on re s et (por). after por h as completed the device will rem a in in i s p mode u ntil r s t i s b ro u ght high. once the initi a l i s p s e ss ion h as ended, the power to the t a rget device m us t b e cycled off a nd on to enter a nother s e ss ion. ?the ss pin s ho u ld not b e left flo a ting d u ring re s et if i s p i s en ab led. ?the i s p en ab le f us e m us t b e s et to a llow progr a mming d u ring a ny re s et period. if the i s p f us e i s di sab led, i s p m a y only b e entered a t por. ?for s t a nd a lone progr a mmer s , r s t m a y b e tied directly to gnd to en su re correct entry into progr a mming mode reg a rdle ss of the device s etting s . 25.2 memory organization the at 8 9lp3240/6440 offer s 64k b yte s of in- s y s tem progr a mm ab le (i s p) nonvol a tile fl as h code memory a nd 8 k b yte s of nonvol a tile fl as h d a t a memory. in a ddition, the device cont a in s a 256- b yte u s er s ign a t u re arr a y a nd a 12 8 - b yte re a d-only atmel s ign a t u re arr a y. the memory org a niz a tion i s s hown in t ab le 25-1 a nd fig u re 25-3 . the memory i s divided into p a ge s of 12 8 b yte s e a ch. a s ingle re a d or write comm a nd m a y only a cce ss h a lf a p a ge (64 b yte s ) in the mem- ory; however, write with au to-er as e comm a nd s will er as e a n entire 12 8 - b yte p a ge even tho u gh they c a n only write one h a lf p a ge. e a ch memory type re s ide s in it s own a ddre ss s p a ce a nd i s a cce ss ed b y comm a nd s s pecific to th a t memory. however, a ll memory type s s h a re the sa me p a ge s ize. u s er config u r a tion f us e s a re m a pped as a row in the memory, with e a ch b yte repre s enting one f us e. from a progr a mming s t a ndpoint, f us e s a re tre a ted the sa me as norm a l code b yte s except they a re not a ffected b y chip er as e. f us e s c a n b e en ab led a t a ny time b y writing 00h to the a ppropri a te loc a tion s in the f us e row. however, to di sab le a f us e, i.e. s et it to ffh, the entire f us e row m us t b e er as ed a nd then reprogr a mmed. the progr a mmer s ho u ld re a d the s t a te of a ll the f us e s into a tempor a ry loc a tion, modify tho s e f us e s which need to b e di sab led, then i ssu e a f us e write with a u to-er as e comm a nd us ing the tempor a ry d a t a . lock b it s a re tre a ted in a s imi- l a r m a nner to f us e s except they m a y only b e er as ed ( u nlocked) b y chip er as e. table 25-1. at 8 9lp3240/6440 memory org a niz a tion memory capacity page size # pages address range code 32kb (at 8 9lp3240) 12 8 b yte s 256 0000h ? 7fffh 64kb (at 8 9lp6440) 12 8 b yte s 512 0000h ? ffffh data 8 192 b yte s 12 8 b yte s 64 1000h ? 3fffh u s er s ign a t u re 256 b yte s 12 8 b yte s 2 0000h ? 00ffh atmel s ign a t u re 12 8 b yte s 12 8 b yte s 1 0000h ? 007fh
160 3706c?micro?2/11 at89lp3240/6440 figure 25-3. at 8 9lp6440 memory org a niz a tion 25.3 command format progr a mming comm a nd s con s i s t of a n opcode b yte, two a ddre ss b yte s , a nd zero or more d a t a b yte s . in a ddition, a ll comm a nd p a cket s m us t s t a rt with a two- b yte pre a m b le of aah a nd 55h. the pre a m b le incre as e s the noi s e imm u nity of the progr a mming interf a ce b y m a king it more dif- fic u lt to i ssu e u nintention a l comm a nd s . fig u re 25-4 on p a ge 161 s how s a s implified flow ch a rt of a comm a nd s eq u ence. a sa mple comm a nd p a cket i s s hown in fig u re 25-5 on p a ge 161 . the ss pin define s the p a cket fr a me. ss m us t b e b ro u ght low b efore the fir s t b yte in a comm a nd i s s ent a nd b ro u ght ba ck high a fter the fin a l b yte in the comm a nd h as b een s ent. the comm a nd i s not complete u ntil ss ret u rn s high. comm a nd b yte s a re i ssu ed s eri a lly on mo s i. d a t a o u tp u t b yte s a re received s eri- a lly on mi s o. p a cket s of v a ri ab le length a re su pported b y ret u rning ss high when the fin a l req u ired b yte h as b een tr a n s mitted. in s ome c as e s comm a nd b yte s h a ve a don?t c a re v a l u e. don?t c a re b yte s in the middle of a p a cket m us t b e tr a n s mitted. don?t c a re b yte s a t the end of a p a cket m a y b e ignored. p a ge oriented in s tr u ction s a lw a y s incl u de a f u ll 16- b it a ddre ss . the higher order b it s s elect the p a ge a nd the lower order b it s s elect the b yte within th a t p a ge. the at 8 9lp3240/6440 a lloc a te s 6 b it s for b yte a ddre ss , 1 b it for low/high h a lf p a ge s election a nd 9 b it s for p a ge a ddre ss . the h a lf p a ge to b e a cce ss ed i s a lw a y s fixed b y the p a ge a ddre ss a nd h a lf s elect as tr a n s mitted. the b yte a ddre ss s pecifie s the s t a rting a ddre ss for the fir s t d a t a b yte. after e a ch d a t a b yte h as b een tr a n s mitted, the b yte a ddre ss i s incremented to point to the next d a t a b yte. thi s a llow s a p a ge comm a nd to line a rly s weep the b yte s within a p a ge. if the b yte a ddre ss i s incremented p as t the l as t b yte in the h a lf p a ge, the b yte a ddre ss will roll over to the fir s t b yte in the sa me h a lf p a ge. while lo a ding b yte s into the p a ge bu ffer, overwriting previo us ly lo a ded b yte s will re su lt in d a t a corr u ption. page 511 low page 510 low user fuse row user signature array atmel signature array code memory 00 3 f 0000 ffff page 0 low 1000 3 fff data memory page 511 high page 510 high 40 7f page 6 3 high page 6 3 low page 0 low page 0 low page 1 low page 0 high page 1 high page 0 low page 1 low page 0 low page 1 high page 1 high page 0 high page 0 high 00 3 f page buffer
161 3706c?micro?2/11 at89lp3240/6440 for a su mm a ry of a v a il ab le comm a nd s , s ee t ab le 25-2 on p a ge 162 . figure 25-4. comm a nd s eq u ence flow ch a rt figure 25-5. i s p comm a nd p a cket ( s eri a l) figure 25-6. i s p comm a nd p a cket (p a r a llel) inp u t pre a m b le 2 (55h) inp u t opcode inp u t addre ss high byte inp u t addre ss low byte inp u t/o u tp u t d a t a addre ss +1 inp u t pre a m b le 1 (aah) 70 654321 7 0 654321 7 0 654321 7 0 654321 70 654321 ss s ck mo s i mi s o pre a m b le 2 opcode addre ss high addre ss low d a t a in d a t a o u t x xxx pre a m b le 1 x ss s ck p0 55h opcode addre ss high addre ss low aah d a t a in oe write p0 55h opcode addre ss high addre ss low aah d a t a o u t oe read
162 3706c?micro?2/11 at89lp3240/6440 note s :1.progr a m en ab le m us t b e the first comm a nd i ssu ed a fter entering into progr a mming mode. 2. p a r a llel en ab le s witche s the interf a ce from s eri a l to p a r a llel form a t u ntil r s t ret u rn s high. 3. any n u m b er of d a t a b yte s from 1 to 64 m a y b e written/re a d. the intern a l a ddre ss i s incremented b etween e a ch b yte. 4. e a ch b yte a ddre ss s elect s one f us e or lock b it. d a t a b yte s m us t b e 00h or ffh. 5. s ee t ab le 25-5 on p a ge 164 for f us e definition s . 6. s ee t ab le 25-4 on p a ge 163 for lock bit definition s . 7. atmel signature bytes : 8 . symbol key : table 25-2. progr a mming comm a nd su mm a ry command opcode addr high addr low data 0 data n progr a m en ab le (1) 1010 1100 0101 0011 ? ? ? p a r a llel en ab le (2) 1010 1100 0011 0101 ? ? ? chip er as e 1000 1010 ???? re a d s t a t us 0110 0000 xxxx x xxx xxxx xxxx s t a t us o u t lo a d p a ge b u ffer (3) 0101 0001 xxxx xxxx 00 bb bbbb d a t a in 0 ... d a t a in n write code p a ge (3) 0101 0000 aaaa aaaa asbb bbbb d a t a in 0 ... d a t a in n write code p a ge with a u to-er as e (3) 0111 0000 aaaa aaaa asbb bbbb d a t a in 0 ... d a t a in n re a d code p a ge (3) 0011 0000 aaaa aaaa asbb bbbb d a t a o u t 0 ... d a t a o u t n write d a t a p a ge (3) 1101 0000 000 a aaaa asbb bbbb d a t a in 0 ... d a t a in n write d a t a p a ge with a u to-er as e (3) 1101 0010 000 a aaaa asbb bbbb d a t a in 0 ... d a t a in n re a d d a t a p a ge (3) 1011 0000 000 a aaaa asbb bbbb d a t a o u t 0 ... d a t a o u t n write u s er f us e s (3)(4)(5) 1110 0001 0000 0000 00 bb bbbb d a t a in 0 ... d a t a in n write u s er f us e s with a u to-er as e (3)(4)(5) 1111 0001 0000 0000 00 bb bbbb d a t a in 0 ... d a t a in n re a d u s er f us e s (3)(4)(5) 0110 0001 0000 0000 00 bb bbbb d a t a o u t 0 ... d a t a o u t n write lock bit s (3)(4)(6) 1110 0100 0000 0000 00 bb bbbb d a t a in 0 ... d a t a in n re a d lock bit s (3)(4)(6) 0110 0100 0000 0000 00 bb bbbb d a t a o u t 0 ... d a t a o u t n write u s er s ign a t u re p a ge (3) 0101 0010 0000 0000 asbb bbbb d a t a in 0 ... d a t a in n write u s er s ign a t u re p a ge with a u to-er as e (3) 0111 0010 0000 0000 asbb bbbb d a t a in 0 ... d a t a in n re a d u s er s ign a t u re p a ge (3) 0011 0010 0000 0000 asbb bbbb d a t a o u t 0 ... d a t a o u t n re a d atmel s ign a t u re p a ge (3)(7) 0011 1000 0000 0000 0 sbb bbbb d a t a o u t 0 ... d a t a o u t n addre ss : 0000h 0001h 0002h at 8 9lp3240: 1eh 32h fch at 8 9lp6440: 1eh 64h ffh a :p a ge addre ss bit s :h a lf p a ge s elect bit b : byte addre ss bit x: don?t c a re bit
163 3706c?micro?2/11 at89lp3240/6440 25.4 status register the c u rrent s t a te of the memory m a y b e a cce ss ed b y re a ding the s t a t us regi s ter. the s t a t us reg- i s ter i s s hown in t ab le 25-3 . 25.5 data polling the at 8 9lp3240/6440 implement s data polling to indic a te the end of a progr a mming cycle. while the device i s bus y, a ny a ttempted re a d of the l as t b yte written will ret u rn the d a t a b yte with the m s b complemented. once the progr a mming cycle h as completed, the tr u e v a l u e will b e a cce ss i b le. d u ring er as e the d a t a i s assu med to b e ffh a nd data polling will ret u rn 7fh. when writing m u ltiple b yte s in a p a ge, the data v a l u e will b e the l as t d a t a b yte lo a ded b efore progr a mming b egin s , not the written b yte with the highe s t phy s ic a l a ddre ss within the p a ge. 25.6 flash security the at 8 9lp3240/6440 provide s two lock bit s for fl as h code a nd d a t a memory s ec u rity. lock b it s c a n b e left u nprogr a mmed (ffh) or progr a mmed (00h) to o b t a in the protection level s li s ted in t ab le 25-4 . lock b it s c a n only b e er as ed ( s et to ffh) b y chip er as e. lock b it mode 2 di sab le s progr a mming of a ll memory s p a ce s , incl u ding the u s er s ign a t u re arr a y a nd u s er config u r a tion f us e s . u s er f us e s m us t b e progr a mmed b efore en ab ling lock b it mode 2 or 3. lock b it mode 3 implement s mode 2 a nd a l s o b lock s re a d s from the code a nd d a t a memorie s ; however, re a d s of the u s er s ign a t u re arr a y, atmel s ign a t u re arr a y, a nd u s er config u r a tion f us e s a re s till a llowed. the lock bit s will not di sab le fdata or iap progr a mming initi a ted b y the a pplic a tion s oftw a re. table 25-3. s t a t us regi s ter ? ??? load s ucce ss wrtinh bu s y bit76543210 symbol function load lo a d fl a g. cle a red low b y the lo a d p a ge bu ffer comm a nd a nd s et high b y the next memory write. thi s fl a g s ign a l s th a t the p a ge bu ffer w as previo us ly lo a ded with d a t a b y the lo a d p a ge bu ffer comm a nd. s ucce ss su cce ss fl a g. cle a red low a t the s t a rt of a progr a mming cycle a nd will only b e s et high if the progr a mming cycle complete s witho u t interr u ption from the b rowno u t detector. wrtinh write inhi b it fl a g. cle a red low b y the b rowno u t detector (bod) whenever progr a mming i s inhi b ited d u e to v dd f a lling b elow the minim u m req u ired progr a mming volt a ge. if a bod epi s ode occ u r s d u ring progr a mming, the s ucce ss fl a g will rem a in low a fter the cycle i s complete. bu s y b us y fl a g. cle a red low whenever the memory i s bus y progr a mming or if write i s c u rrently inhi b ited. table 25-4. lock bit protection mode s program lock bits (by address) mode 00h 01h protection mode 1 ffh ffh no progr a m lock fe a t u re s 200hffhf u rther progr a mming of the fl as h i s di sab led 3 00h 00h f u rther progr a mming of the fl as h i s di sab led a nd verify (re a d) i s a l s o di sab led; ocd i s di sab led
164 3706c?micro?2/11 at89lp3240/6440 25.7 user configuration fuses the at 8 9lp3240/6440 incl u de s 11 us er f us e s for config u r a tion of the device. e a ch f us e i s a cce ss ed a t a s ep a r a te a ddre ss in the u s er f us e row as li s ted in t ab le 25-5 . f us e s a re cle a red b y progr a mming 00h to their loc a tion s . progr a mming ffh to a f us e loc a tion will c aus e th a t f us e to m a int a in it s previo us s t a te. to s et a f us e ( s et to ffh) the f us e row m us t b e er as ed a nd then reprogr a mmed us ing the f us e write with a u to-er as e comm a nd. the def au lt s t a te for a ll f us e s i s ffh. note s : 1. the def au lt s t a te for a ll f us e s i s ffh. 2. ch a nge s to the s e f us e s will only t a ke effect a fter a device por. 3. ch a nge s to the s e f us e s will only t a ke effect a fter the i s p s e ss ion termin a te s b y b ringing r s t high. table 25-5. u s er config u r a tion f us e definition s address fuse name description 00 ? 01h clock s o u rce ? c s [0:1] (2) s elect s s o u rce for the s y s tem clock: c s 1c s 0 s elected s o u rce 00h 00h high s peed cry s t a l o s cill a tor (xtal) 00h ffh low s peed cry s t a l o s cill a tor (xtal) ffh 00h extern a l clock on xtal1 (xclk) ffh ffh intern a l rc o s cill a tor (irc) 02 ? 03h s t a rt- u p time ? s ut[0:1] s elect s time-o u t del a y for the por/bod/pwd w a ke- u p period: s ut1 s ut0 s elected time-o u t 00h 00h 1 m s (xtal); 16 s (xclk/irc) 00h ffh 2 m s (xtal); 512 s (xclk/irc) ffh 00h 4 m s (xtal); 1 m s (xclk/irc) ffh ffh 16 m s (xtal); 4 m s (xclk/irc) 04h re s et pin en ab le (3) ffh: r s t pin f u nction s as re s et 00h: r s t pin f u nction s as gener a l p u rpo s e i/o 05h brown-o u t detector en ab le ffh: brown-o u t detector en ab led 00h: brown-o u t detector di sab led 06h on-chip de bu g en ab le ffh: on-chip de bu g di sab led 00h: on-chip de bu g en ab led 07h i s p en ab le (3) ffh: in- s y s tem progr a mming en ab led 00h: in- s y s tem progr a mming di sab led (en ab led a t por only) 0 8 hu s er s ign a t u re progr a mming ffh: progr a mming of u s er s ign a t u re di sab led 00h: progr a mming of u s er s ign a t u re en ab led 09h tri s t a te port s ffh: i/o port s s t a rt in inp u t-only mode (tri s t a ted) a fter re s et 00h: i/o port s s t a rt in q uas i- b idirection a l mode a fter re s et 0ah ocd interf a ce s elect ffh: f as t two-wire interf a ce 00h: do not us e 0bh in-applic a tion progr a mming ffh: in-applic a tion progr a mming di sab led 00h: in-applic a tion progr a mming en ab led
165 3706c?micro?2/11 at89lp3240/6440 25.8 user signature and analog configuration the u s er s ign a t u re arr a y cont a in s 256 b yte s of non-vol a tile memory in two 12 8 - b yte p a ge s . the fir s t p a ge of the u s er s ign a t u re arr a y (0000h?007fh) i s a v a il ab le for s eri a l n u m b er s , firmw a re revi s ion inform a tion, d a te code s or other us er p a r a meter s . the u s er s ign a t u re arr a y m a y only b e written b y a n extern a l device when the u s er s ign a t u re progr a mming f us e i s en ab led. when the f us e i s en ab led, chip er as e will a l s o er as e the fir s t p a ge of the a rr a y. when the f us e i s di s - ab led, the a rr a y i s not a ffected b y write or er as e comm a nd s . progr a mming of the s ign a t u re arr a y c a n a l s o b e di sab led b y the lock bit s . however, re a ding the s ign a t u re i s a lw a y s a llowed a nd the a rr a y s ho u ld not b e us ed to s tore s ec u rity s en s itive inform a tion. the u s er s ign a t u re arr a y m a y b e modified d u ring exec u tion thro u gh the in-applic a tion progr a mming interf a ce, reg a rdle ss of the s t a te of the u s er s ign a t u re progr a mming f us e or lock bit s , provided th a t the iap f us e i s en ab led. note th a t the a ddre ss of the u s er s ign a t u re arr a y, as s een b y the iap interf a ce, eq ua l s the u s er s ign a t u re a ddre ss pl us 256 (0100h?01ffh in s te a d of 0000h? 00ffh). the s econd p a ge of the u s er s ign a t u re arr a y (00 8 0h?00ffh) cont a in s a n a log config u r a tion p a r a meter s for the at 8 9lp3240/6440. e a ch b yte repre s ent s a p a r a meter as li s ted in t ab le 25-6 a nd i s pre s et in the f a ctory. the p a r a meter s a re re a d a t por a nd the device i s config u red a ccordingly. the s econd p a ge of the a rr a y i s not a ffected b y chip er as e. other b yte s in thi s p a ge m a y b e us ed as a ddition a l s ign a t u re s p a ce; however, c a re s ho u ld b e t a ken to pre s erve the p a r a meter v a l u e s when modifying other b yte s . 25.9 programming interface timing thi s s ection det a il s gener a l s y s tem timing s eq u ence s a nd con s tr a int s for entering or exiting in- s y s tem progr a mming as well as p a r a meter s rel a ted to the s eri a l peripher a l interf a ce d u ring i s p. the gener a l timing p a r a meter s for the following w a veform fig u re s a re li s ted in s ection ?tim- ing p a r a meter s ? on p a ge 169 . 25.9.1 power-up sequence exec u te thi s s eq u ence to enter progr a mming mode immedi a tely a fter power- u p. in the r s t pin i s di sab led or if the i s p f us e i s di sab led, thi s i s the only method to enter progr a mming ( s ee ?extern a l re s et? on p a ge 35 ). 1. apply power b etween vdd a nd gnd pin s . r s t s ho u ld rem a in low. 2. w a it a t le as t t pwrup . a nd drive ss high. 3. w a it a t le as t t s ut for the intern a l power-on re s et to complete. the v a l u e of t s ut will depend on the c u rrent s etting s of the device. 4. s t a rt progr a mming s e ss ion. table 25-6. an a log config u r a tion definition s address parameter name description 00 8 0h rc o s cill a tor c a li b r a tion byte the rc c a li b r a tion byte control s the freq u ency of the intern a l rc o s cill a tor. the freq u ency i s inver s ely proportion a l to the c a li b r a tion v a l u e su ch th a t higher v a l u e s re su lt in lower freq u encie s . a copy of the f a ctory- s et c a li b r a tion v a l u e i s s tored a t loc a tion 000 8 h of the atmel s ign a t u re.
166 3706c?micro?2/11 at89lp3240/6440 figure 25-7. s eri a l progr a mming power- u p s eq u ence 25.9.2 power-down sequence exec u te thi s s eq u ence to power-down the device after progr a mming. 1. drive s ck low. 2. w a it a t le as t t ss d a nd b ring ss high. 3. tri s t a te mo s i. 4. w a it a t le as t t ss z a nd then tri s t a te ss a nd s ck. 5. w a it no more th a n t pwrdn a nd power off vdd. figure 25-8. s eri a l progr a mming power-down s eq u ence 25.9.3 isp start sequence exec u te thi s s eq u ence to exit cpu exec u tion mode a nd enter i s p mode when the device h as p ass ed power-on re s et a nd i s a lre a dy oper a tion a l. 1. drive r s t low. 2. drive ss high. 3. w a it t rlz + t s tl . 4. s t a rt progr a mming s e ss ion. v dd r s t ss s ck high z mi s o high z mo s i t pwrup t por + t s ut t z ss v dd r s t ss s ck high z mi s o high z mo s i t pwrdn t ss d t ss z
167 3706c?micro?2/11 at89lp3240/6440 figure 25-9. in- s y s tem progr a mming (i s p) s t a rt s eq u ence 25.9.4 isp exit sequence exec u te thi s s eq u ence to exit i s p mode a nd re su me cpu exec u tion mode. 1. drive s ck low. 1. w a it a t le as t t ss d a nd drive ss high. 2. tri s t a te mo s i. 3. w a it a t le as t t ss z a nd b ring r s t high. 4. tri s t a te s ck. 5. w a it t rhz a nd tri s t a te ss . figure 25-10. in- s y s tem progr a mming (i s p) exit s eq u ence note: the w a veform s on thi s p a ge a re not to s c a le. 25.9.5 serial peripheral interface the s eri a l peripher a l interf a ce ( s pi) i s a b yte-oriented f u ll-d u plex s ynchrono us s eri a l comm u ni- c a tion ch a nnel. d u ring in- s y s tem progr a mming, the progr a mmer a lw a y s a ct s as the s pi m as ter a nd the t a rget device a lw a y s a ct s as the s pi s l a ve. the t a rget device receive s s eri a l d a t a on mo s i a nd o u tp u t s s eri a l d a t a on mi s o. the progr a mming interf a ce implement s a s t a nd a rd s pi port with a fixed d a t a order a nd for in- s y s tem progr a mming, b yte s a re tr a n s ferred m s b fir s t as s hown in fig u re 25-11 . the s ck ph as e a nd pol a rity follow s pi clock mode 0 (cpol = 0, t s tl v dd r s t ss s ck high z mo s i high z mi s o xtal1 t rlz t z ss t ss e v dd r s t ss s ck high z mo s i high z mi s o xtal1 t ss z t ss d t rhz
168 3706c?micro?2/11 at89lp3240/6440 cpha = 0) where b it s a re sa mpled on the ri s ing edge of s ck a nd o u tp u t on the f a lling edge of s ck. for more det a iled timing inform a tion s ee fig u re 25-12 . figure 25-11. i s p byte s eq u ence figure 25-12. s eri a l progr a mming interf a ce timing figure 25-13. p a r a llel progr a mming interf a ce timing 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 mo s i mi s o s ck d a t a sa mpled t sr t sse t slsh t sov t sf t sox t ssd t sck t shsl t soe t soh t sih t sis ss sck miso mosi t sr t sse t slsh t sf t pox t ssd t sck t shsl t pov t poe t pih t pis ss sck p0 oe t poh
169 3706c?micro?2/11 at89lp3240/6440 25.9.6 timing parameters the timing p a r a meter s for fig u re 25-7 , fig u re 25- 8 , fig u re 25-9 , fig u re 25-10 , fig u re 25-12 a nd fig u re 25-13 a re s hown in t ab le . note: 1. t s ck i s independent of t clcl . table 25-7. progr a mming interf a ce timing p a r a meter s symbol parameter min max units t clcl s y s tem clock cycle time 0 60 n s t pwrup power on to ss high time 10 s t por power-on re s et time 100 s t pwrdn ss tr i s t a te to power off 1 s t rlz r s t low to i/o tri s t a te t clcl 2 t clcl n s t s tl r s t low s ettling time 100 n s t rhz r s t high to ss tr i s t a te 0 2 t clcl n s t s ck s eri a l clock cycle time 200 (1) n s t s h s l clock high time 75 n s t s l s h clock low time 50 n s t s r ri s e time 25 n s t s f f a ll time 25 n s t s i s s eri a l inp u t s et u p time 10 n s t s ih s eri a l inp u t hold time 10 n s t s oh s eri a l o u tp u t hold time 10 n s t s ov s eri a l o u tp u t v a lid time 35 n s t pi s p a r a llel inp u t s et u p time 10 n s t pih p a r a llel inp u t hold time 10 n s t poh p a r a llel o u tp u t hold time 10 n s t pov p a r a llel o u tp u t v a lid time 35 n s t s oe s eri a l o u tp u t en ab le time 10 n s t s ox s eri a l o u tp u t di sab le time 25 n s t poe p a r a llel o u tp u t en ab le time 10 n s t pox p a r a llel o u tp u t di sab le time 25 n s t ss e ss en ab le le a d time t s l s h n s t ss d ss di sab le l a g time t s l s h n s t z ss s ck s et u p to ss low 25 n s t ss z s ck hold a fter ss high 25 n s t wr write cycle time 2.5 m s t awr write cycle with a u to-er as e time 5 m s t er s chip er as e cycle time 7.5 m s
170 3706c?micro?2/11 at89lp3240/6440 26. electrical characteristics note s : 1. under s te a dy s t a te (non-tr a n s ient) condition s , i ol m us t b e extern a lly limited as follow s : m a xim u m i ol per port pin: 10 ma m a xim u m tot a l i ol for a ll o u tp u t pin s : 15 ma if i ol exceed s the te s t condition, v ol m a y exceed the rel a ted s pecific a tion. pin s a re not g ua r a nteed to s ink c u rrent gre a ter th a n the li s ted te s t condition s . 2. minim u m v dd for power-down i s 2v. 26.1 absolute maximum ratings* oper a ting temper a t u re ................................... -40c to + 8 5c *notice: s tre ss e s b eyond tho s e li s ted u nder ?a bs ol u te m a xim u m r a ting s ? m a y c aus e perm a nent d a m- a ge to the device. thi s i s a s tre ss r a ting only a nd f u nction a l oper a tion of the device a t the s e or a ny other condition s b eyond tho s e indic a ted in the oper a tion a l s ection s of thi s s pecific a tion i s not implied. expo su re to abs ol u te m a xim u m r a ting condition s for extended period s m a y a ffect device reli ab ility. s tor a ge temper a t u re ..................................... -65c to +150c volt a ge on any pin with re s pect to gro u nd......-0.7v to +3.6v m a xim u m oper a ting volt a ge ............................................ 3.6v dc c u rrent per i/o pin .................................................. 10 ma dc tot a l c u rrent ....................................................... 200.0 ma 26.2 dc characteristics t a = -40c to 8 5c, v dd = 2.4v to 3.6v ( u nle ss otherwi s e noted) symbol parameter condition min max units v il inp u t low-volt a ge -0.5 0.2 v dd - 0.1 v v ih inp u t high-volt a ge 0.2 v dd + 0.9 v dd + 0.5 v v ol o u tp u t low-volt a ge (1) i ol = 10 ma, v dd = 2.7v, t a = 8 5c 0.5 v v oh o u tp u t high-volt a ge with we a k p u ll- u p s en ab led i oh = -50 a, v dd = 3v 10% 1.35 v i oh = -30 a 0.7 v dd v i oh = -12 a 0. 8 5 v dd v v oh1 o u tp u t high-volt a ge with s trong p u ll- u p s en ab led i oh = -10 ma, t a = 8 5c 0.6 v dd i oh = -5 ma, t a = 8 5c 0. 8 v dd i il logic 0 inp u t c u rrent v in = 0.45v -50 a i tl logic 1 to 0 tr a n s ition c u rrent v in = 1.5v, v dd = 3v 10% -250 a i li inp u t le a k a ge c u rrent 0 < v in < v dd 10 a r r s t re s et p u ll- u p re s i s tor 50 150 k c io pin c a p a cit a nce te s t freq. = 1 mhz, t a = 25c 10 pf c decoupling su pply deco u pling c a p a cit a nce minim u m per vdd pin = 20 nf 60 nf i cc power su pply c u rrent active mode, 12 mhz, v dd = 3.6v 8 .5 ma idle mode, 12 mhz, v dd = 3.6v p1.0 & p1.1 = 0v or v dd 3ma power-down mode (2) v dd = 3.6v, p1.0 & p1.1 = 0v or v dd 5a v dd = 3v, p1.0 & p1.1 = 0v or v dd 2a
171 3706c?micro?2/11 at89lp3240/6440 26.3 safe operating conditions 26.3.1 speed fig u re 26-1 s how s the sa fe oper a ting freq u encie s for the at 8 9lp3240/6440 ver sus su pply volt- a ge. the device i s only g au r a nteed to oper a te correctly within thi s a re a . note th a t the on-chip brown-o u t detector (bod) h as a minim u m thre s hold of 1. 8 v. s y s tem s th a t rely on thi s bod to prevent incorrect oper a tion d u e to power lo ss s ho u ld only oper a te a t 12 mhz or b elow. s y s tem s a t higher freq u encie s m a y req u ire a n extern a l bod. figure 26-1. oper a ting freq u ency v s . v dd 26.3.2 power dissipation figure 26-2. m a xim u m oper a ting c u rrent v s . temper a t u re (v dd = 3.3v) 26.4 typical characteristics the following ch a rt s s how typic a l b eh a vior. the s e fig u re s a re not te s ted d u ring m a n u f a ct u ring. all c u rrent con su mption me asu rement s a re performed with a ll i/o pin s config u red as q uas i- b idi- rection a l (with intern a l p u ll- u p s ). a s q ua re w a ve gener a tor with r a il-to-r a il o u tp u t i s us ed as a n extern a l clock s o u rce for con su mption ver sus freq u ency me asu rement s . 0 1.8 2.7 3.6 12 20 24 2.4 vdd (v) frequency (mhz) -40 0 100 200 temperature (c) i output (ma) 50 150 65 85 pdip tqfp plcc mlf/qfn 68 75 79 67 74 121
172 3706c?micro?2/11 at89lp3240/6440 26.4.1 supply current (internal oscillator) figure 26-3. active su pply c u rrent v s . v dd ( 8 mhz intern a l o s cill a tor) figure 26-4. idle su pply c u rrent v s . v dd ( 8 mhz intern a l o s cill a tor) 2.4 2.7 3.0 3.3 3.6 3.5 4.0 4.5 5.0 5.5 6.0 6.5 85c -40c 25c vcc (v) icc (ma) active supp l y current vs. vcc 8mhz internal oscillator 2.4 2.7 3.0 3.3 3.6 1.00 1.25 1.50 1.75 2.00 85c -40c 25c vcc (v) icc (ma) idle supply current vs. vcc 8mhz internal oscillator
173 3706c?micro?2/11 at89lp3240/6440 26.4.2 supply current (external clock) figure 26-5. active su pply c u rrent v s . freq u ency figure 26-6. idle su pply c u rrent v s . freq u ency 0 5 10 15 20 25 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 3.6 v 3.3 v 3.0 v 2.7 v 2.4 v frequency (mhz) icc (ma) active supply current vs. frequency external clock source 0 5 10 15 20 25 0 1 2 3 4 5 3.6 v 3.3 v 3.0 v 2.7 v 2.4 v frequency (mhz) icc (ma) idle supply current vs. frequency external clock source
174 3706c?micro?2/11 at89lp3240/6440 26.4.3 quasi-bidirectional input figure 26-7. q uas i- b idirection a l inp u t tr a n s ition c u rrent a t 3.3v 26.4.4 quasi-bidirectional output figure 26-8. q uas i-bidirection a l o u tp u t i-v s o u rce ch a r a cteri s tic a t 3v 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 -120 -100 -80 -60 -40 -20 0 85c -40c 25c v il (v) i tl ( a) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 -100 -80 -60 -40 -20 0 85c -40c 25c v oh (v) i oh ( a)
175 3706c?micro?2/11 at89lp3240/6440 26.4.5 push-pull output figure 26-9. p us h-p u ll o u tp u t i-v s o u rce ch a r a cteri s tic a t 3v figure 26-10. p us h-p u ll o u tp u t i-v s ink ch a r a cteri s tic a t 3v note: the i ol /v ol ch a r a cteri s tic a pplie s to p us h-p u ll, q uas i-bidirection a l a nd open-dr a in mode s . 26.5 clock characteristics figure 26-11. extern a l clock drive w a veform 2.4 2.5 2.6 2.7 2.8 2.9 3.0 -10 -8 -6 -4 -2 0 85c -40c 25c v oh1 (v) i oh1 (ma) 0.0 0.1 0.2 0.3 0.4 0.5 0 2 4 6 8 10 85c -40c 25c v ol (v) i ol (ma)
176 3706c?micro?2/11 at89lp3240/6440 the v a l u e s s hown in the s e t ab le s a re v a lid for t a = -40c to 8 5c a nd v dd = 2.4 to 3.6v, u nle ss otherwi s e noted. note: 1. no w a it s t a te ( s ingle-cycle) exec u tion s peed figure 26-12. typic a l intern a l o s cill a tor freq u ency v s . vcc table 26-1. extern a l clock p a r a meter s symbol parameter v dd = 2.4v to 3.6v v dd = 2.7v to 3.6v units min max min max 1/t clcl o s cill a tor freq u ency (1) 020025mhz t clcl clock period 50 40 n s t chcx extern a l clock high time 12 12 n s t clcx extern a l clock low time 12 12 n s t clch extern a l clock ri s e time 5 5 n s t chcl extern a l clock f a ll time 5 5 n s table 26-2. clock ch a r a cteri s tic s symbol parameter condition min max units f xtal cry s t a l o s cill a tor freq u ency low s peed o s cill a tor 10 100 khz high s peed o s cill a tor 0.5 24 mhz f rc intern a l o s cill a tor freq u ency t a = 25c; v dd = 3.0v 7.92 8 .0 8 mhz v dd = 2.4 to 3.6v 7. 8 0 8 .20 mhz 2.4 2.7 3.0 3.3 3.6 7.80 7.85 7.90 7.95 8.00 8.05 8.10 -40c 0c 25c 70c 85c vcc (v) frequency (mhz)
177 3706c?micro?2/11 at89lp3240/6440 figure 26-13. typic a l cry s t a l o s cill a tor s wing with q ua rtz cry s t a l a nd c1=c2, t a = 25c note: 1. repl a cing c a p a citor c1 with a re s i s tor r1 of 4 m re su lt s in s imil a r s wing level s on xtal1. figure 26-14. typic a l cry s t a l o s cill a tor s wing with cer a mic re s on a tor a nd c1=c2, t a = 25c 4 8 12 16 20 2.0 2.5 3.0 3.5 4.0 3.6v 15pf 3.6v 10pf 3.6v 5pf 2.4v 15pf 2.4v 10pf 2.4v 5pf frequency (mhz) vpp on xtal1 (v) 4 8 12 16 20 1.0 1.5 2.0 2.5 3.0 3.5 4.0 3.6v 15pf 3.6v 10pf 3.6v 5pf 2.4v 15pf 2.4v 10pf 2.4v 5pf frequency (mhz) vpp on xtal1 (v)
178 3706c?micro?2/11 at89lp3240/6440 26.6 reset characteristics the v a l u e s s hown in thi s t ab le a re v a lid for t a = -40c to 8 5c a nd v dd = 2.4 to 3.6v, u nle ss otherwi s e noted. 26.7 external data memory characteristics the v a l u e s s hown in thi s t ab le a re v a lid for t a = -40c to 8 5c a nd v dd = 2.4 to 3.6v, u nle ss otherwi s e noted. under oper- a ting condition s , lo a d c a p a cit a nce for port 0 a nd ale = 100 pf; lo a d c a p a cit a nce for a ll other o u tp u t s = 8 0 pf. p a r a meter s refer to fig u re 26-15 a nd fig u re 26-16 . note s :1.thi s assu me s 50% clock d u ty cycle. the h a lf period depend s on the clock high v a l u e t chcx (high d u ty cycle). 2. thi s assu me s 50% clock d u ty cycle. the h a lf period depend s on the clock low v a l u e t clcx (low d u ty cycle). table 26-3. re s et ch a r a cteri s tic s symbol parameter condition min max units r r s t re s et p u ll- u p re s i s tor 50 150 k v por power-on re s et thre s hold 1.3 1.6 v v bod brown-o u t detector thre s hold 1. 8 2.0 v v bh brown-o u t detector hy s tere s i s 200 300 mv t por power-on re s et del a y 135 150 s t wdtr s t w a tchdog re s et p u l s e width 16t clcl n s table 26-4. extern a l d a t a memory ch a r a cteri s tic s symbol parameter variable oscillator units min max 1/t clcl o s cill a tor freq u ency 0 24 mhz t lhll ale p u l s e width (3) t clcl - d n s t avll addre ss v a lid to ale low 0.5t clcl - d (1) n s t llax addre ss hold a fter ale low 0.5t clcl - d (2) n s t rlrh rd p u l s e width (4) t clcl - d n s t wlwh wr p u l s e width (4) t clcl - d n s t rldv rd low to v a lid d a t a in t clcl - d n s t rhdx d a t a hold a fter rd 0n s t rhdz d a t a flo a t a fter rd t clcl - d n s t lldv ale low to v a lid d a t a in 2t clcl - d n s t avdv addre ss to v a lid d a t a in 2.5t clcl - d (1) n s t llwl ale low to rd or wr low t clcl - d t clcl + d n s t avwl addre ss to rd or wr low 1.5t clcl - d (1) n s t qvwx d a t a v a lid to wr tr a n s ition 0.5t clcl - d (1) n s t qvwh d a t a v a lid to wr high 1.5t clcl - d (1) n s t whqx d a t a hold a fter wr 0.5t clcl - d (2) n s t rlaz rd low to addre ss flo a t -0.5t clcl + d (1) n s t whax addre ss hold a fter rd or wr high 0.5t clcl - d (2) n s t whlh rd or wr high to ale high (5) t clcl - d t clcl + d n s
179 3706c?micro?2/11 at89lp3240/6440 3. p a r a meter t lhll a pplie s only when ale s =1. 4. the s tro b e p u l s e width m a y b e lengthened b y 1, 2 or 3 a ddition a l t clcl us ing w a it s t a te s . 5. p a r a meter t whlh a pplie s only when ale s = 0, or when two movx in s tr u ction s occ u r in su cce ss ion. figure 26-15. extern a l d a t a memory re a d cycle figure 26-16. extern a l d a t a memory write cycle 26.8 serial peripheral interface timing the v a l u e s s hown in the s e t ab le s a re v a lid for t a = -40c to 8 5c a nd v dd = 2.4 to 3.6v, u nle ss otherwi s e noted. table 26-5. s pi master ch a r a cteri s tic s symbol parameter min max units t clcl o s cill a tor period 41.6 n s t s ck s eri a l clock cycle time 4t clcl n s t s h s l clock high time t s ck /2 - 25 n s t s l s h clock low time t s ck /2 - 25 n s t s r ri s e time 25 n s t s f f a ll time 25 n s t lhll ale data i n a0 - a7 a8 - a15 from dph or p2.0 - p2.7 p2 p2 rd port 0 port 2 t llwl t rlrh t avll t llax t rlaz t rhdz t avwl t whlh t whax t avdv t lldv t rldv t rhdx t lhll ale data out a0 - a7 a8 - a15 from dph or p2.0 - p2.7 p2 p2 wr port 0 port 2 t llwl t wlwh t avll t llax t qvwx t qvwh t whqx t avwl t whlh t whax
180 3706c?micro?2/11 at89lp3240/6440 figure 26-17. s pi m as ter timing (cpha = 0) t s i s s eri a l inp u t s et u p time 10 n s t s ih s eri a l inp u t hold time 10 n s t s oh s eri a l o u tp u t hold time 10 n s t s ov s eri a l o u tp u t v a lid time 35 n s table 26-5. s pi master ch a r a cteri s tic s symbol parameter min max units table 26-6. s pi slave ch a r a cteri s tic s symbol parameter min max units t clcl o s cill a tor period 41.6 n s t s ck s eri a l clock cycle time 4t clcl n s t s h s l clock high time 1.5 t clcl - 25 n s t s l s h clock low time 1.5 t clcl - 25 n s t s r ri s e time 25 n s t s f f a ll time 25 n s t s i s s eri a l inp u t s et u p time 10 n s t s ih s eri a l inp u t hold time 10 n s t s oh s eri a l o u tp u t hold time 10 n s t s ov s eri a l o u tp u t v a lid time 35 n s t s oe o u tp u t en ab le time 10 n s t s ox o u tp u t di sab le time 25 n s t ss e s l a ve en ab le le a d time 10 n s t ss d s l a ve di sab le l a g time 0 n s ss sck (cpol = 0) sck (cpol = 1) miso mosi t sr t sck t slsh t slsh t shsl t shsl t soh t sf t sis t sih t sov
181 3706c?micro?2/11 at89lp3240/6440 figure 26-18. s pi s l a ve timing (cpha = 0) figure 26-19. s pi m as ter timing (cpha = 1) figure 26-20. s pi s l a ve timing (cpha = 1) t sr t sse t slsh t shsl t sov t sf t sox t ssd t sck t slsh t shsl t soe t soh t sih t sis ss sck (cpol = 0) sck (cpol= 1) miso mosi t shsl t slsh t shsl t slsh t sck t soh t sf t sr t sis t sov t sih ss sck (cpol = 0) sck (cpol = 1) miso mosi ss sck (cpol = 0) sck (cpol = 1) miso mosi t sck t sse t shsl t shsl t slsh t slsh t ssd t sih t sis t soe t sov t soh t sox t sf t sr
182 3706c?micro?2/11 at89lp3240/6440 26.9 two-wire serial in terface characteristics t ab le 26-7 de s cri b e s the req u irement s for device s connected to the two-wire s eri a l b us . the at 8 9lp3240/6440 two-wire s eri a l interf a ce meet s or exceed s the s e req u irement s u nder the noted condition s . the v a l u e s s hown in thi s t ab le a re v a lid for t a = -40c to 8 5c a nd v dd = 2.4 to 3.6v, u nle ss otherwi s e noted. timing s ym b ol s refer to fig u re 26-21 . note s :1.in at 8 9lp3240/6440, thi s p a r a meter i s ch a r a cterized a nd not 100% te s ted. 2. req u ired only for f s cl > 100 khz. table 26-7. two-wire s eri a l b us req u irement s symbol parameter condition min max units v il inp u t low-volt a ge -0.5 0.3 v dd v v ih inp u t high-volt a ge 0.7 v dd v dd + 0.5 v v hy s (1) hy s tere s i s of s chmitt trigger inp u t s 0.05 v dd (2) ?v v ol (1) o u tp u t low-volt a ge 3 ma s ink c u rrent 0 0.4 v t r (1) ri s e time for b oth s da a nd s cl 20 + 0.1c b (3)(2) 300 n s t of (1) o u tp u t f a ll time from v ihmin to v ilm a x 10 pf < c b < 400 pf (3) 20 + 0.1c b (3)(2) 250 n s t s p (1) s pike s su ppre ss ed b y inp u t filter 0 50 (2) n s i i inp u t c u rrent e a ch i/o pin 0.1v dd < v i < 0.9v dd -10 10 a c i (1) c a p a cit a nce for e a ch i/o pin ? 10 pf f s cl s cl clock freq u ency f ck (4) > 16f s cl 0 400 khz rp v a l u e of p u ll- u p re s i s tor f s cl 100 khz f s cl > 100 khz t hd; s ta hold time (repe a ted) s tart condition f s cl 100 khz 4.0 ? s f s cl > 100 khz 0.6 ? s t low low period of the s cl clock f s cl 100 khz 4.7 ? s f s cl > 100 khz 1.3 ? s t high high period of the s cl clock f s cl 100 khz 4.0 ? s f s cl > 100 khz 0.6 ? s t s u; s ta s et- u p time for a repe a ted s tart condition f s cl 100 khz 4.7 ? s f s cl > 100 khz 0.6 ? s t hd;dat d a t a hold time f s cl 100 khz 0 3.45 s f s cl > 100 khz 0 0.9 s t s u;dat d a t a s et u p time f s cl 100 khz 250 ? n s f s cl > 100 khz 100 ? n s t s u; s to s et u p time for s top condition f s cl 100 khz 4.0 ? s f s cl > 100 khz 0.6 ? s t buf b us free time b etween a s top a nd s ta rt condition f s cl 100 khz 4.7 ? s v dd 0.4v ? 3ma ---------------------------- - 1000n s c b ------------------- v dd 0.4v ? 3ma ---------------------------- - 300n s c b --------------- -
183 3706c?micro?2/11 at89lp3240/6440 3. c b = c a p a cit a nce of one bus line in pf. 4. f ck = cpu clock freq u ency figure 26-21. two-wire s eri a l b us timing figure 26-22. s hift regi s ter mode timing w a veform t s u; s ta t low t high t low t of t hd; s ta t hd;dat t s u;dat t s u; s to t buf s cl s da t r 26.10 serial port timing : shift register mode the v a l u e s in thi s t ab le a re v a lid for v dd = 2.4v to 3.6v a nd lo a d c a p a cit a nce = 8 0 pf. symbol parameter smod1 = 0 smod1 = 1 units min max min max t xlxl s eri a l port clock cycle time 4t clcl -15 2t clcl -15 s t qvxh o u tp u t d a t a s et u p to clock ri s ing edge 3t clcl -15 t clcl -15 n s t xhqx o u tp u t d a t a hold a fter clock ri s ing edge t clcl -15 t clcl -15 n s t xhdx inp u t d a t a hold a fter clock ri s ing edge 0 0 n s t xhdv inp u t d a t a v a lid to clock ri s ing edge 15 15 n s 01234567 v a lid v a lid v a lid v a lid v a lid v a lid v a lid v a lid clock write to s buf o u tp u t d a t a cle a r ri inp u t d a t a s mod1 = 0 01234567 v a lid v a lid v a lid v a lid v a lid v a lid v a lid v a lid clock write to s buf o u tp u t d a t a cle a r ri inp u t d a t a s mod1 = 1
184 3706c?micro?2/11 at89lp3240/6440 26.11 dual analog compar ator characteristics the v a l u e s s hown in thi s t ab le a re v a lid for t a = -40c to 8 5c a nd v dd = 2.4 to 3.6v, u nle ss otherwi s e noted. figure 26-23. an a log reference volt a ge typic a l ch a r a cteri s tic s table 26-8. d ua l an a log comp a r a tor ch a r a cteri s tic s symbol parameter condition min max units v cm common mode inp u t volt a ge gnd v dd v v o s inp u t off s et volt a ge v dd = 3.6v 20 mv v aref an a log reference volt a ge 1.23 1.36 v v ref reference delt a volt a ge 90 120 mv t cmp comp a r a tor prop a g a tion del a yv in+ ? v in- = 20mv; v dd = 2.4v 200 n s t aref reference s ettling time 3 s 2.4 2.7 3.0 3.3 3.6 1.1 1.2 1.3 1.4 1.5 vref+ 85c vref+ 25c vref+ -40c vref 85c vref 25c vref -40c vref- -40c vref- 25c vref- 85c vcc (v) v ref (v)
185 3706c?micro?2/11 at89lp3240/6440 26.12 dadc characteristics the v a l u e s s hown in the s e t ab le s a re v a lid for t a = -40c to 8 5c a nd v dd = 2.4 to 3.6v, u nle ss otherwi s e noted. . table 26-9. adc ch a r a cteri s tic s symbol parameter conditi on min typical max units re s ol u tion 10 bit s a bs ol u te acc u r a cy (incl u ding inl, dnl, q ua ntiz a tion error, g a in a nd off s et error) 4l s b integr a l non-line a rity (inl) 4 l s b differenti a l non-line a rity (dnl) 4l s b g a in error 16 l s b off s et error 16 l s b t ack clock period 500 n s t adc conver s ion time 13t ack 14t ack + 2t clcl n s v ref reference volt a ge extern a l reference v dd /2 - 0.2 v dd /2 v dd /2 + 0.2 v intern a l reference 0.9 1.0 1.1 v v in s ingle-ended inp u t volt a ge v dd /2 - v ref v dd /2 + v ref v v cmi differenti a l inp u t common mode volt a ge gnd v dd v v di differenti a l inp u t volt a ge 0 v ref v r in an a log inp u t re s i s t a nce 10 k r mux an a log m u x re s i s t a nce 10 k c s /h sa mple & hold c a p a cit a nce 3 pf table 26-10. dac ch a r a cteri s tic s symbol parameter conditi on min typical max units re s ol u tion 10 bit s t ack clock period t ack t clcl 500 n s t dac conver s ion time 11t ack 12t ack + 2t clcl n s v ref reference volt a ge extern a l reference v dd /2 - 0.2 v dd /2 v dd /2 + 0.2 v intern a l reference 0.9 1.0 1.1 v v in s ingle-ended inp u t volt a ge v dd /2 - v ref v dd /2 + v ref v v cmo differenti a l o u tp u t common mode volt a ge v dd /2 - 0.2 v dd /2 v dd /2 + 0.2 v v do differenti a l o u tp u t volt a ge 0 v ref v r out an a log o u tp u t re s i s t a nce 100 200 k
186 3706c?micro?2/11 at89lp3240/6440 26.13 test conditions 26.13.1 ac testing input/output waveform figure 26-24. ac testing input/output waveform (1) note: 1. ac inp u t s d u ring te s ting a re driven a t v dd - 0.5v for a logic ?1? a nd 0.45v for a logic ?0?. timing me asu rement s a re m a de a t v ih min. for a logic ?1? a nd v il m a x. for a logic ?0?. 26.13.2 float waveform figure 26-25. float waveform (1) note: 1. for timing p u rpo s e s , a port pin i s no longer flo a ting when a 100 mv ch a nge from lo a d volt a ge occ u r s . a port pin b egin s to flo a t when 100 mv ch a nge from the lo a ded v oh /v ol level occ u r s . 26.13.3 i cc test condition: active mode figure 26-26. connection di a gr a m for i cc active me asu rement. all other pin s a re di s connected for a ctive su pply c u rrent me asu rement s a ll port s a re config u red in q uas i- b idirection a l mode. timer s 0, 1 a nd 2 a re config u red to b e free r u nning in their def au lt timer mode s . the cpu exe- c u te s a s imple r a ndom n u m b er gener a tor th a t a cce ss e s ram, the s fr bus a nd exerci s e s the alu a nd h a rdw a re m u ltiplier. xtal2 rst v dd v dd i cc xtal1 gnd (nc) clock signal v dd
187 3706c?micro?2/11 at89lp3240/6440 26.13.4 i cc test condition: idle mode figure 26-27. connection di a gr a m for i cc idle me asu rement. all other pin s a re di s connected 26.13.5 clock signal waveform for i cc tests figure 26-28. clock s ign a l w a veform for i cc in active a nd idle mode s , t clch = t chcl = 5 n s 26.13.6 i cc test condition: power-down mode figure 26-29. connection di a gr a m for i cc power-down me asu rement.all other pin s a re di s - connected, v dd = 2v to 3.6v xtal2 rst v dd v dd i cc xtal1 gnd (nc) clock signal v dd v cc - 0.5v 0.45v 0.2 v cc - 0.1v 0.7 v cc t chcx t chcx t clch t chcl t clcl xtal2 rst v dd v dd i cc xtal1 gnd (nc) v dd
188 3706c?micro?2/11 at89lp3240/6440 27. ordering information 27.1 green package op tion (pb/halide-free) code flash speed (mhz) power supply ordering code package operation range 32kb 20 2.4v to 3.6v at 8 9lp3240-20au at 8 9lp3240-20pu 44a 40p6 ind us tri a l (-40 c to 8 5 c) at 8 9lp3240-20ju at 8 9lp3240-20mu 44j 44m1 64kb 20 2.4v to 3.6v at 8 9lp6440-20au at 8 9lp6440-20pu 44a 40p6 at 8 9lp6440-20ju at 8 9lp6440-20mu 44j 44m1 package types 44a 44-le a d, thin pl as tic q ua d fl a t p a ck a ge (tqfp) 40p6 40-le a d, 0.600? wide, pl as tic d ua l inline p a ck a ge (pdip) 44j 44-le a d, pl as tic j-le a ded chip c a rrier (plcc) 44m1 44-p a d, 7 x 7 x 1.0 mm body, pl as tic very thin q ua d fl a t no le a d p a ck a ge (vqfn/mlf)
189 3706c?micro?2/11 at89lp3240/6440 28. packaging information 28.1 44a ? tqfp 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 44a, 44-lead, 10 x 10 mm body size, 1.0 mm body thickness, 0.8 mm lead pitch, thin profile plastic quad flat package (tqfp) b 44a 10/5/2001 pin 1 identifier 0?~7? pin 1 l c a1 a2 a d1 d e e1 e b common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference ms-026, variation acb. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. dimensions d1 and e1 are maximum plastic body size dimensions including mold mismatch. 3. lead coplanarity is 0.10 mm maximum. a 1.20 a1 0.05 0.15 a2 0.95 1.00 1.05 d 11.75 12.00 12.25 d1 9.90 10.00 10.10 note 2 e 11.75 12.00 12.25 e1 9.90 10.00 10.10 note 2 b 0.30 0.45 c 0.09 0.20 l 0.45 0.75 e 0.80 typ
190 3706c?micro?2/11 at89lp3240/6440 28.2 40p6 ? pdip 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 40p6 , 40-lead (0.600"/15.24 mm wide) plastic dual inline package (pdip) b 40p6 09/28/01 pin 1 e1 a1 b ref e b1 c l seating plane a 0?~ 15? d e eb common dimensions (unit of measure = mm) symbol min nom max note a 4.826 a1 0.381 d 52.070 52.578 note 2 e 15.240 15.875 e1 13.462 13.970 note 2 b 0.356 0.559 b1 1.041 1.651 l 3.048 3.556 c 0.203 0.381 eb 15.494 17.526 e 2.540 typ notes: 1. this package conforms to jedec reference ms-011, variation ac. 2. dimensions d and e1 do not include mold flash or protrusion. mold flash or protrusion shall not exceed 0.25 mm (0.010").
191 3706c?micro?2/11 at89lp3240/6440 28.3 44j ? plcc note s : 1. thi s p a ck a ge conform s to jedec reference m s -01 8 , v a ri a tion ac. 2. dimen s ion s d1 a nd e1 do not incl u de mold protr us ion. allow ab le protr us ion i s .010"(0.254 mm) per s ide. dimen s ion d1 a nd e1 incl u de mold mi s m a tch a nd a re me asu red a t the extreme m a teri a l condition a t the u pper or lower p a rting line. 3. le a d copl a n a rity i s 0.004" (0.102 mm) m a xim u m. a 4.191 ? 4.572 a1 2.2 8 6 ? 3.04 8 a2 0.50 8 ? ? d 17.399 ? 17.653 d1 16.510 ? 16.662 note 2 e 17.399 ? 17.653 e1 16.510 ? 16.662 note 2 d2/e2 14.9 8 6 ? 16.002 b 0.660 ? 0. 8 13 b1 0.330 ? 0.533 e 1.270 typ common dimensions (unit of me asu re = mm) symbol min nom max note 1.14(0.045) x 45? pin no. 1 identifier 1.14(0.045) x 45? 0.51(0.020)max 0.31 8 (0.0125) 0.191(0.0075) a2 45? max (3x) a a1 b1 d2/e2 b e e1 e d1 d 44j , 44-le a d, pl as tic j-le a ded chip c a rrier (plcc) b 44j 10/04/01 2325 orch a rd p a rkw a y sa n jo s e, ca 95131 title drawing no. r rev.
192 3706c?micro?2/11 at89lp3240/6440 28.4 44m1 ? vqfn/mlf title drawing no. gpc rev. packa g e drawin g contact: packagedrawings@atmel.com 44m1 zws h 44m1, 44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, 5.20 mm exposed pad, thermally enhanced plastic very thin quad flat no lead package (vqfn) 9/26/08 common dimen s ion s (unit of measure = mm) s ymbol min nom max note a 0.80 0.90 1.00 a1 ? 0.02 0.05 a 3 0.20 ref b 0.18 0.2 3 0. 3 0 d d2 5.00 5.20 5.40 6.90 7.00 7.10 6.90 7.00 7.10 e e2 5.00 5.20 5.40 e 0.50 bsc l 0.59 0.64 0.69 k 0.20 0.26 0.41 note: jedec standard mo-220, fig. 1 (saw singulation) vkkd- 3 . top view s ide view bottom view d e marked pin# 1 id e2 d2 b e pin #1 corner l a1 a 3 a seating plane pin #1 triangle pin #1 chamfer (c 0. 3 0) option a option b pin #1 notch (0.20 r) option c k k 1 2 3
193 3706c?micro?2/11 at89lp3240/6440 29. revision history revision no. history revi s ion a ? s eptem b er 2009 ? initi a l rele as e revi s ion b? s eptem b er 2010 ? removed prelimin a ry s t a t us ? upd a ted ?dc ch a r a cteri s tic s ? on p a ge 170 ? upd a ted ?typic a l ch a r a cteri s tic s ? on p a ge 171 ? ren a med avdd to vdd revi s ion c? fe b r ua ry 2011 ? added s ection ? s y s tem config u r a tion? on p a ge 8 ? added the at 8 9lp3240 device ? upd a ted o s cill a tor connection di a gr a m, fig u re 6-1 on p a ge 31
194 3706c?micro?2/11 at89lp3240/6440
i 3706c?micro?2/11 at89lp3240/6440 table of contents features ................ ................ .............. ............... .............. .............. ............ 1 1 pin configurations ..... ................ ................. ................ ................. ............ 2 1.1 40p6: 40-le a d pdip ...........................................................................................2 1.2 44a: 44-le a d tqfp (top view) .........................................................................2 1.3 44j: 44-le a d plcc ............................................................................................3 1.4 44m1: 44-p a d vqfn/mlf .................................................................................3 1.5 pin de s cription ..................................................................................................4 2 overview ............ ................ ................ ............... .............. .............. ............ 6 2.1 block di a gr a m ...................................................................................................7 2.2 s y s tem config u r a tion ........................................................................................ 8 2.3 comp a ri s on to s t a nd a rd 8 051 ...........................................................................9 3 memory organization ......... .............. ............... .............. .............. .......... 11 3.1 progr a m memory .............................................................................................11 3.2 intern a l d a t a memory ......................................................................................12 3.3 extern a l d a t a memory .....................................................................................13 3.4 extended s t a ck ...............................................................................................20 3.5 in-applic a tion progr a mming (iap) ...................................................................21 4 special function registers ..... ................ ................. ................ ............. 22 5 enhanced cpu ............. ................. ................ ................. .............. .......... 23 5.1 m u ltiply?acc u m u l a te unit (mac) .....................................................................24 5.2 enh a nced d ua l d a t a pointer s .........................................................................25 5.3 in s tr u ction s et exten s ion s ...............................................................................30 6 system clock ............. ................ ................. ................ ................. .......... 31 6.1 cry s t a l o s cill a tor .............................................................................................31 6.2 extern a l clock s o u rce .....................................................................................32 6.3 intern a l rc o s cill a tor ......................................................................................32 6.4 s y s tem clock o u t ............................................................................................32 6.5 s y s tem clock divider ......................................................................................32 7 reset ............. ................ ................. ................ ................. .............. .......... 33 7.1 power-on re s et ...............................................................................................33 7.2 brown-o u t re s et ..............................................................................................35 7.3 extern a l re s et .................................................................................................35
ii 3706c?micro?2/11 at89lp3240/6440 table of contents (continued) 7.4 w a tchdog re s et ..............................................................................................36 7.5 s oftw a re re s et ................................................................................................36 8 power saving modes .......... .............. ............... .............. .............. .......... 36 8 .1 idle mode .........................................................................................................36 8 .2 power-down mode ...........................................................................................37 8 .3 red u cing power con su mption ........................................................................3 8 9 interrupts ........ ................. ................ ................. .............. .............. .......... 39 9.1 interr u pt re s pon s e time .................................................................................41 10 i/o ports ............... ................ .............. ............... .............. .............. .......... 45 10.1 port config u r a tion ............................................................................................45 10.2 port an a log f u nction s .....................................................................................4 8 10.3 port re a d-modify-write ...................................................................................4 8 10.4 port altern a te f u nction s ..................................................................................49 11 enhanced timer 0 and timer 1 with pwm .. ................. .............. .......... 51 11.1 mode 0 ? v a ri ab le width timer/co u nter .........................................................52 11.2 mode 1 ? 16- b it a u to-relo a d timer/co u nter ...................................................52 11.3 mode 2 ? 8 - b it a u to-relo a d timer/co u nter .....................................................53 11.4 mode 3 ? 8 - b it s plit timer ...............................................................................53 11.5 p u l s e width mod u l a tion ...................................................................................56 12 enhanced timer 2 ............... .............. ............... .............. .............. .......... 60 12.1 timer 2 regi s ter s ............................................................................................61 12.2 c a pt u re mode ..................................................................................................62 12.3 a u to-relo a d mode ...........................................................................................63 12.4 b au d r a te gener a tor ......................................................................................67 12.5 freq u ency gener a tor (progr a mm ab le clock o u t) ...........................................6 8 13 compare/capture array ..... .............. ............... .............. .............. .......... 69 13.1 cca regi s ter s .................................................................................................70 13.2 inp u t c a pt u re mode .........................................................................................72 13.3 o u tp u t comp a re mode ....................................................................................75 13.4 p u l s e width mod u l a tion mode .........................................................................77 14 external interrupts .......... ................ ................. .............. .............. .......... 82 15 general-purpose interrupts .... ................ ................. ................ ............. 83
iii 3706c?micro?2/11 at89lp3240/6440 table of contents (continued) 16 serial interface (uart) .............. ................. ................ ................. .......... 85 16.1 m u ltiproce ss or comm u nic a tion s ..................................................................... 8 5 16.2 b au d r a te s ...................................................................................................... 8 7 16.3 more a b o u t mode 0 ......................................................................................... 8 9 16.4 more a b o u t mode 1 .........................................................................................92 16.5 more a b o u t mode s 2 a nd 3 .............................................................................94 16.6 fr a ming error detection ..................................................................................97 16.7 a u tom a tic addre ss recognition ......................................................................97 17 enhanced serial peripheral interface ....... ................ ................. .......... 98 17.1 m as ter oper a tion ...........................................................................................100 17.2 s l a ve oper a tion .............................................................................................101 17.3 pin config u r a tion ...........................................................................................101 17.4 s eri a l clock timing ........................................................................................104 18 two-wire serial inte rface .................... .............. .............. ............ ........ 105 1 8 .1 d a t a tr a n s fer a nd fr a me form a t ..................................................................106 1 8 .2 m u lti-m as ter b us s y s tem s , ar b itr a tion a nd s ynchroniz a tion .........................10 8 1 8 .3 overview of the twi mod u le .........................................................................110 1 8 .4 regi s ter overview .........................................................................................112 1 8 .5 u s ing the twi ................................................................................................113 1 8 .6 tr a n s mi ss ion mode s .....................................................................................115 19 dual analog comparators ..... ................ ................. ................ ............. 126 19.1 an a log inp u t m u xe s .......................................................................................127 19.2 intern a l reference volt a ge ............................................................................12 8 19.3 comp a r a tor interr u pt de b o u ncing .................................................................12 8 20 digital-to-analog/analog-to-digital c onverter ................ .................. 133 20.1 adc oper a tion ..............................................................................................135 20.2 dac oper a tion ..............................................................................................136 20.3 clock s election ..............................................................................................137 20.4 s t a rting a conver s ion ....................................................................................137 20.5 noi s e con s ider a tion s ....................................................................................13 8 21 programmable watchdog timer ................ ................ .............. ........... 141 21.1 s oftw a re re s et ..............................................................................................142
iv 3706c?micro?2/11 at89lp3240/6440 table of contents (continued) 22 instruction set summary ... .............. ............... .............. .............. ........ 143 22.1 in s tr u ction s et exten s ion s .............................................................................147 23 register index ....... ................. ................ ................. ................ ............. 153 24 on-chip debug system ...... .............. ............... .............. .............. ........ 155 24.1 phy s ic a l interf a ce ..........................................................................................155 24.2 s oftw a re bre a kpoint s ....................................................................................156 24.3 limit a tion s of on-chip de bu g .......................................................................156 25 programming the flash memo ry ................. .............. .............. ........... 157 25.1 phy s ic a l interf a ce ..........................................................................................157 25.2 memory org a niz a tion ....................................................................................159 25.3 comm a nd form a t ..........................................................................................160 25.4 s t a t us regi s ter ..............................................................................................163 25.5 data polling .................................................................................................163 25.6 fl as h s ec u rity ................................................................................................163 25.7 u s er config u r a tion f us e s ..............................................................................164 25. 8 u s er s ign a t u re a nd an a log config u r a tion .....................................................165 25.9 progr a mming interf a ce timing ......................................................................165 26 electrical characteristics ... .............. ............... .............. .............. ........ 170 26.1 a bs ol u te m a xim u m r a ting s * .........................................................................170 26.2 dc ch a r a cteri s tic s .........................................................................................170 26.3 sa fe oper a ting condition s ............................................................................171 26.4 typic a l ch a r a cteri s tic s ..................................................................................171 26.5 clock ch a r a cteri s tic s .....................................................................................175 26.6 re s et ch a r a cteri s tic s ....................................................................................17 8 26.7 extern a l d a t a memory ch a r a cteri s tic s ..........................................................17 8 26. 8s eri a l peripher a l interf a ce timing .................................................................179 26.9 two-wire s eri a l interf a ce ch a r a cteri s tic s ......................................................1 8 2 26.10 s eri a l port timing: s hift regi s ter mode ........................................................1 8 3 26.11 d ua l an a log comp a r a tor ch a r a cteri s tic s ......................................................1 8 4 26.12 dadc ch a r a cteri s tic s ....................................................................................1 8 5 26.13 te s t condition s ..............................................................................................1 8 6 27 ordering information .......... .............. ............... .............. .............. ........ 188 27.1 green p a ck a ge option (p b /h a lide-free) ........................................................1 88
v 3706c?micro?2/11 at89lp3240/6440 table of contents (continued) 28 packaging information .......... ................ ................. ................ ............. 189 2 8 .1 44a ? tqfp ...................................................................................................1 8 9 2 8 .2 40p6 ? pdip ..................................................................................................190 2 8 .3 44j ? plcc ...................................................................................................191 2 8 .4 44m1 ? vqfn/mlf .......................................................................................192 29 revision history ....... ................ ................ ................. ................ ........... 193 table of contents.......... ................. ................ ................. ................ ........... i
3706c?micro?2/11 atmel corporation 2325 orch a rd p a rkw a y sa n jo s e, ca 95131 u s a tel : (+1) (40 8 ) 441-0311 fax : (+1) (40 8 ) 4 8 7-2600 www. a tmel.com 8 051@ a tmel.com atmel asia limited unit 1-5 & 16, 19/f bea tower, millenni u m city 5 41 8 kw u n tong ro a d kw u n tong, kowloon hong kong tel : (+ 8 52) 2245-6100 fax : (+ 8 52) 2722-1369 atmel munich gmbh b us ine ss c a mp us p a rkring 4 d- 8 574 8 g a rching b . m u nich germany tel : (+49) 8 9-31970-0 fax : (+49) 8 9-3194621 atmel japan 9f, tonet su s hink a w a bldg. 1-24- 8 s hink a w a ch u o-k u , tokyo 104-0033 japan tel : (+ 8 1) (3) 3523-3551 fax : (+ 8 1) (3) 3523-75 8 1 disclaimer: the inform a tion in thi s doc u ment i s provided in connection with atmel prod u ct s . no licen s e, expre ss or implied, b y e s toppel or otherwi s e, to a ny intellect ua l property right i s gr a nted b y thi s doc u ment or in connection with the sa le of atmel prod u ct s . except as set forth in atmel?s terms and condi- tions of sale located on atmel? s web site, atmel assumes no liability whatsoever and disclaims any express, implied or statutor y warranty relating to its products including, but not limited to , the implied warranty of merchantability, fitness for a particu lar purpose, or non-infringement. in no event shall atmel be liable for any direct, indirect, conseque ntial, punitive, special or i nciden- tal damages (including, without limitation, damages for loss of profits, business interruption, or loss of information) arising out of the use or inability to use this document, even if at mel has been advised of the possibility of such damages. atmel m a ke s no repre s ent a tion s or w a rr a ntie s with re s pect to the a cc u r a cy or completene ss of the content s of thi s doc u ment a nd re s erve s the right to m a ke ch a nge s to s pecific a tion s a nd prod u ct de s cription s a t a ny time witho u t notice. atmel doe s not m a ke a ny commitment to u pd a te the inform a tion cont a ined herein. unle ss s pecific a lly provided otherwi s e, atmel prod u ct s a re not su it ab le for, a nd s h a ll not b e us ed in, au tomotive a pplic a tion s . atmel? s prod u ct s a re not intended, au thorized, or w a rr a nted for us e as component s in a pplic a tion s intended to su pport or sus t a in life. ? 2011 atmel corporation. all rights reserved. atmel ? , atmel logo a nd com b in a tion s thereof, a nd other s a re regi s tered tr a dem a rk s or tr a dem a rk s of atmel corpor a tion or it s subs idi a rie s . other term s a nd prod u ct n a me s m a y b e tr a dem a rk s of other s .

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